docs: ASCII typography and style normalization across all repo text
Replace every em dash with real punctuation (rewrites, not hyphen swaps) in docs, code comments, scripts, configs, and the port records; convert en dashes, curly quotes, ellipsis glyphs, arrows, and section signs to ASCII; drop machine-writing tell phrases from living docs. ADR titles now use a colon. The M2 bring-up DTS model string carried an em dash into the patch series and its record echoes; fixed at both, and the full series re-verified to apply cleanly onto pristine 6.18.46. One comment in freshness.h deliberately names the em dash glyph the UI renders as the unknown mark; that is data, kept as prose naming it. Verified: cargo tests (sim, config-lint, rs485-bridge), shellcheck, both driver MC/DC harnesses, patches-apply.
This commit is contained in:
BFE Engineering
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@@ -1,4 +1,4 @@
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# RV1106 → Linux 6.18 forward-port (self-built, from vendor 5.10)
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# RV1106 -> Linux 6.18 forward-port (self-built, from vendor 5.10)
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**Decision (2026-08-23):** forward-port the RV1106 SoC enablement from the
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Rockchip **vendor 5.10** tree straight to **Linux 6.18 LTS**, ourselves, using **no
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@@ -6,7 +6,7 @@ plan44 code**, built on **our Buildroot 2025.02 LTS + uClibc**. We own the tree.
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## The reality this rests on (verified, not assumed)
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Vanilla mainline (6.6.93 and 6.18) has **zero** RV1106 support — no devicetree, no
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Vanilla mainline (6.6.93 and 6.18) has **zero** RV1106 support: no devicetree, no
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clock driver, no pinctrl data, not one `rv1106` reference in `arch/arm` or
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`drivers/`. So "the newest kernel" is a generic ARM kernel that cannot boot this
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SoC. What we forward-port is the **entire RV1106 BSP**: ~120 files in the vendor
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@@ -16,48 +16,48 @@ it is delivered incrementally, console-first.
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## Method (how each piece is ported)
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- **Framework drivers → sibling-delta.** clk and pinctrl are driven by the shared
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- **Framework drivers -> sibling-delta.** clk and pinctrl are driven by the shared
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rockchip framework (`drivers/clk/rockchip/clk.c`, `pinctrl-rockchip.c`). RV1106's
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siblings **rv1126 and rv1108 exist in BOTH vendor-5.10 and mainline-6.18**, so
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their 5.10→6.18 delta is the exact recipe for how the framework API changed —
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we apply that recipe to rv1106's data (`clk-rv1106.c` = 1284 lines;
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their 5.10->6.18 delta is the exact recipe for how the framework API changed.
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We apply that recipe to rv1106's data (`clk-rv1106.c` = 1284 lines;
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`rv1106-cru.h` clock IDs; the rv1106 pinctrl table). This turns "adapt to APIs
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we have to guess" into "copy a diff a sibling already proves."
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- **SoC-unique code → forward-port + build-fix-build.** `mach-rockchip`
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- **SoC-unique code -> forward-port + build-fix-build.** `mach-rockchip`
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(machine, `rockchip_hptimer`, `rv1106_pm`/`rv1106_sleep.S`), the CRU/GRF glue,
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and the board DT have no sibling; port directly and iterate on the 6.18 build.
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- **Mainline-present drivers → just wire DT + clocks.** 8250-dw UART, dw_mmc
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- **Mainline-present drivers -> just wire DT + clocks.** 8250-dw UART, dw_mmc
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(SDIO/eMMC), dw-apb i2c, rockchip gpio/pinctrl core, pwm, dw-wdt watchdog are all
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in mainline 6.18 — we do **not** port them, we supply the DT nodes + clock/reset
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in mainline 6.18. We do **not** port them, we supply the DT nodes + clock/reset
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phandles and let the mainline drivers bind.
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- **Out-of-tree drivers → port the driver.** AIC8800 wifi (plan44 has none; ours),
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RGA/MPP kernel bits (assess vs need — the 86-Panel has no camera), carrying our
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- **Out-of-tree drivers -> port the driver.** AIC8800 wifi (plan44 has none; ours),
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RGA/MPP kernel bits (assess vs need: the 86-Panel has no camera), carrying our
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Tier-1 SDIO-wakeup fix forward.
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- **Our 4 kernel patches** (panel-mcu-reset/logo, watchdog-enable, usb-otg
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dual-role, recovery-splash) → re-apply against 6.18 (line offsets + some DT
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dual-role, recovery-splash) -> re-apply against 6.18 (line offsets + some DT
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bindings changed).
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## Bring-up milestones (console-first order)
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- **M0 — buildable base.** 6.18.46 tree + our Buildroot/uClibc toolchain builds a
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- **M0: buildable base.** 6.18.46 tree + our Buildroot/uClibc toolchain builds a
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generic ARM kernel; a `rv1106_defconfig` forward-ported from vendor 5.10.
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- **M1 — SoC compiles.** `mach-rockchip` RV1106 select + `clk-rv1106` +
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- **M1: SoC compiles.** `mach-rockchip` RV1106 select + `clk-rv1106` +
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rv1106 pinctrl data + `rv1106-cru.h` compile clean against 6.18 (no boot yet).
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- **M2 — earlycon boot.** DT (`rv1106.dtsi` core) + clk + pinctrl + 8250-dw →
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- **M2: earlycon boot.** DT (`rv1106.dtsi` core) + clk + pinctrl + 8250-dw ->
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kernel prints to the RV1106 UART. The first "it's alive."
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- **M3 — rootfs boot.** dw_mmc + DT → eMMC/SD rootfs, userspace up on our Buildroot.
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- **M4 — display.** VOP2 + the RGB666 720×720 panel + GT911 touch + PWM backlight →
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- **M3: rootfs boot.** dw_mmc + DT -> eMMC/SD rootfs, userspace up on our Buildroot.
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- **M4: display.** VOP2 + the RGB666 720x720 panel + GT911 touch + PWM backlight ->
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the LVGL UI renders.
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- **M5 — wifi + our patches.** AIC8800 SDIO driver ported (+ Tier-1 fix); the 4
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- **M5: wifi + our patches.** AIC8800 SDIO driver ported (+ Tier-1 fix); the 4
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custom kernel patches re-applied.
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- **M6 — the rest.** RGA (UI accel), watchdog, HPMCU coprocessor, USB-OTG dual role.
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- **M6: the rest.** RGA (UI accel), watchdog, HPMCU coprocessor, USB-OTG dual role.
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## Regression (so a 6.18 port doesn't reintroduce the struct-ABI bug class)
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The warden-sdk simulator + MC/DC harness are how we hold the line: `HpmcuSim` and
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the register/`MemBus` seam test the supervisor/reset logic off the ported kernel;
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the `relays-mcdc` pattern extends to each ported driver we own; and a
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**config-lint CI gate** (the class that bricked c8a3 — a load address in unreserved
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**config-lint CI gate** (the class that bricked c8a3: a load address in unreserved
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kernel RAM) checks the DT reservations against the drivers on every build.
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## Layout (this repo)
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@@ -3,39 +3,39 @@
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Booting the self-built 6.18 kernel on real hardware (warden-c8a3), 2026-08-24.
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The build side (zImage + dtb) is in `../rv1106-enablement/`; this is the on-target
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half. **The safe-test framework and the boot-image format below are the reusable
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findings — they worked on the first hardware try.**
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findings: they worked on the first hardware try.**
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## The safe test path (A/B slot _b, never touch _a)
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c8a3 is the desk-connected bench Warden: reachable over its USB-gadget ethernet
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(dev-build dropbear; address and bench credentials live in the private
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deployment notes — use `scp -O`, no sftp-server), plus the serial console at
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deployment notes: use `scp -O`, no sftp-server), plus the serial console at
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115200 and remotely switchable power. It runs an A/B
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firmware (boot_a=mmcblk0p5 / boot_b=mmcblk0p6, 32 MiB each; rootfs_a/_b; AvbABData
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in `misc` sector 4 / byte 2048).
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The test never risks the working system:
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1. Back up `boot_b` (`dd .../by-name/boot_b -> /userdata/boot_b.bak`).
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2. Write the test `boot.img` to **boot_b only** — `_a` (the shipped WardenOS) is
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2. Write the test `boot.img` to **boot_b only**. `_a` (the shipped WardenOS) is
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untouched.
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3. Flip AvbABData to a **one-shot _b**: `craft_ab.py 14 0 1 15 1 0 1` → A(prio14,
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3. Flip AvbABData to a **one-shot _b**: `craft_ab.py 14 0 1 15 1 0 1` -> A(prio14,
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tries0,ok1) B(prio15,tries1,ok0); write to `misc` sector 4. U-Boot's SPL then
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picks _b once, decrements tries→0, and boots it.
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picks _b once, decrements tries->0, and boots it.
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4. If the test kernel fails/hangs, U-Boot auto-reverts to `_a` (SPL: "slot boot
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failed, resetting" → next boot `A/B-slot: _a, successful: 1`). A hung kernel
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failed, resetting" -> next boot `A/B-slot: _a, successful: 1`). A hung kernel
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just needs a Zigbee power-cycle; `_a` boots WardenOS back. **Zero manual
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recovery needed — verified across three failed attempts.**
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recovery needed: verified across three failed attempts.**
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`earlycon=uart8250,mmio32,0xff4c0000` is confirmed correct: it is in the live
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5.10 cmdline, and U-Boot's own DDR probe reports `Adding bank: 0x0 - 0x10000000`
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(256 MiB) — so the M2 DT's memory node and earlycon are right.
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(256 MiB), so the M2 DT's memory node and earlycon are right.
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## The boot-image format (this was the whole fight)
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rockchip U-Boot (this build) needs a very specific `boot.img`, NOT a plain FIT:
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- **External-data FIT.** `mkimage -f its -E -p 0x800`. The FDT metadata stays tiny
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(totalsize ≈ 1536 B, matching boot_a); the kernel/fdt/resource **data is
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(totalsize ~ 1536 B, matching boot_a); the kernel/fdt/resource **data is
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appended** after it. A normal embedded-data FIT (totalsize = whole image) is
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rejected with `FIT: No fit blob` / `No FIT image`.
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- **A `resource` (multi) sub-image is mandatory.** rockchip reads the DTB via the
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@@ -43,62 +43,62 @@ rockchip U-Boot (this build) needs a very specific `boot.img`, NOT a plain FIT:
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with `resource_tool --pack`. Without it: `Failed to load DTB, ret=-19`.
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- **Sysmem sentinel load addresses.** fdt `load=0xffffff00`, kernel
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`load=entry=0xffffff01`; U-Boot's sysmem places them (it chose kernel@0x8000,
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fdt@0xc00000). Real low addresses collided → "No fit blob".
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fdt@0xc00000). Real low addresses collided -> "No fit blob".
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- `CONFIG_FIT_SIGNATURE` is **off** in this U-Boot, so the image need not be
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signed. Template: `sdk/sysdrv/source/kernel/boot.its`; builder recipe:
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`sdk/project/scripts/mk-fitimage.sh` (`mkimage -E -p 0x800`).
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With the correct format, U-Boot loaded my kernel + my DTB and printed my DT model
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string (`Model: WardenOS 86-Panel (RV1106) — M2 earlycon bring-up`), then
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string (`Model: WardenOS 86-Panel (RV1106), M2 earlycon bring-up`), then
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`Starting kernel ...`.
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## Result: [x] M2 achieved — the 6.18 kernel boots on hardware
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## Result: [x] M2 achieved, the 6.18 kernel boots on hardware
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Six attempts, each auto-recovering to `_a`, then a clean boot:
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```
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[0.000000] Linux version 6.18.46 … #2 SMP
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[0.000000] Linux version 6.18.46 ... #2 SMP
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[0.000000] CPU: ARMv7 Processor [410fc075]
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[0.000000] OF: fdt: Machine model: WardenOS 86-Panel (RV1106) — M2 earlycon bring-up
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[0.000000] OF: fdt: Machine model: WardenOS 86-Panel (RV1106), M2 earlycon bring-up
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[0.000000] earlycon: uart8250 at MMIO32 0xff4c0000
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[0.000000] cma: Reserved 64 MiB at 0x0c000000
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[0.040693] Calibrating delay loop … 48.00 BogoMIPS ← arch timer up
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[0.040693] Calibrating delay loop ... 48.00 BogoMIPS <- arch timer up
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[0.343810] pinctrl core: initialized pinctrl subsystem
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[1.968703] ff4c0000.serial: ttyS2 … is a 16550A ← 8250 on our CRU clock
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[1.968703] ff4c0000.serial: ttyS2 ... is a 16550A <- 8250 on our CRU clock
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```
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Two more bugs, found via the DEBUG_LL rebuild (`DEBUG_LL_UART_8250`, PHYS
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0xff4c0000, shift 2, 32-bit word + `earlyprintk` — the decompressor prints
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0xff4c0000, shift 2, 32-bit word + `earlyprintk`, the decompressor prints
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pre-MMU), then fixed:
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- **DTB overrun → `r2=0` / `invalid dtb`.** The multi_v7 zImage decompresses to
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- **DTB overrun -> `r2=0` / `invalid dtb`.** The multi_v7 zImage decompresses to
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~20 MiB from 0x8000, overrunning the DTB at 0xc00000, so the decompressor handed
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the kernel a null DTB pointer. Fix: place the fdt high — `load=0x08000000` in the
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the kernel a null DTB pointer. Fix: place the fdt high (`load=0x08000000`) in the
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FIT `.its` (see `boot5.its`). The real fix is a lean defconfig; multi_v7 is bloat.
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- **`grf_ctx` NULL deref in clk-rv1106.** `rockchip_clk_register_branches(grf_ctx,…)`
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- **`grf_ctx` NULL deref in clk-rv1106.** `rockchip_clk_register_branches(grf_ctx,...)`
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crashed because the minimal DT had no `rockchip,rv1106-grf-cru` node to set
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`grf_ctx`. Fix: add the `grf-clock-controller` child to the grf syscon (now in
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`dts/rv1106-warden-m2.dts`).
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**Console baud gotcha:** `console=ttyS2,115200`. earlycon is readable at 115200
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(U-Boot leaves uart2 there), but the vendor's 1.5M console rate is garbage on the
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CP2102 bench adapter — so the M2 DT pins 115200 for readable bring-up; production
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CP2102 bench adapter, so the M2 DT pins 115200 for readable bring-up; production
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overrides to 1.5M.
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## M3 (same session): [x] the full WardenOS runs on the 6.18 kernel
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Adding the eMMC `dw_mmc` node (`mmc@ffa90000`, clocks from cru + grf_cru) was the
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only change M3 needed — the mmc/ext4 drivers are already in-config. The kernel
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only change M3 needed: the mmc/ext4 drivers are already in-config. The kernel
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enumerated the eMMC at HS200, mounted the ext4 rootfs, ran `/sbin/init`, and
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started every WardenOS daemon. A serial root login confirms `uname -a` →
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started every WardenOS daemon. A serial root login confirms `uname -a` ->
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`Linux warden-c8a3 6.18.46 armv7l`, with `warden-flared/-modbus/-mikrotik/-asic/
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-ui/-flight` all running. Expected M4/M5 gaps show cleanly: the 5.10 aic8800 `.ko`
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won't load (vermagic → M5), and there's no backlight/framebuffer yet (→ M4).
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won't load (vermagic -> M5), and there's no backlight/framebuffer yet (-> M4).
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**Console lesson applied:** with `console=ttyS2,115200` the whole boot is readable
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on the CP2102 (the 1.5M vendor rate is garbage on it). Serial login uses the same
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`c8a3_run.py` helper (dev-build bench credentials, see private deployment notes)
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as the 5.10 firmware — the userspace is unchanged.
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as the 5.10 firmware: the userspace is unchanged.
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Next: M4 (VOP2 display + panel + touch), M5 (AIC8800 SDIO port + our 4 patches),
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M6 (RGA/watchdog/HPMCU/USB-OTG); plus a lean defconfig + Buildroot-on-6.18 cleanup.
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