kernel/rv1106: HPMCU mailbox 100% VERIFIED + open NPU driver VERIFIED

MAILBOX (fully open A7<->RISC-V SCR1 round-trip, 5/5 exact echoes on c8a3):
- rockchip-mailbox.c: rv1106 has 1 shared IRQ, not 4/channel -> added
  rv1106_drv_data{num_chans=1} + compatible (rk3368 fallback assumed 4 -> probe
  failed 'IRQ index 1 not found').
- clk-rv1106.c: CLK_CORE_MCU (SCR1 core clock) marked CLK_IGNORE_UNUSED -
  6.18's clk_disable_unused() was switching off the coprocessor clock so a
  loaded firmware never ran (5.10 left it on).
- Open SCR1 echo firmware (scr1-echo/, 154B RV32IMC) + load/test scripts;
  A2B_INTEN on the MCU side + CMD-then-DAT (DAT=doorbell) order. Loaded via the
  proven hpmcu.rs SRAM path; do NOT kill warden-flared (dw-wdt). mailbox/VERIFIED.md.

NPU (open GPL rknpu 0.9.2 kernel driver on 6.18):
- DT fix: base npu node lacks interrupt-names, driver requests IRQ byname
  'npu_irq' -> probe bailed -ENXIO. Added interrupt-names='npu_irq'.
- Verified: [drm] Initialized rknpu 0.9.2 on minor 1; /dev/dri/card1;
  rknpu_version_test PASS (0.9.2 + hw version, full power/clock/reset path).
- Honest ceiling: open compute (regcmd compiler) is a from-scratch ~person-year
  RE project, no RV1106 prior art; ship the driver, no blob. npu/VERIFIED.md.

DRIVER-PARITY + CAPABILITIES-AUDIT updated; dts snapshot refreshed.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf

kernel/rv1106-enablement/mailbox/scr1-echo/start.S

@@ -0,0 +1,27 @@
+/*
+ * HPMCU watchdog entry. The BootROM-style loader (or flared's runtime
+ * loader) points CORE_SGRF_HPMCU_BOOT_ADDR here and releases the SCR1 core
+ * from CORECRU reset; there is no CRT, no interrupts, machine mode only.
+ */
+	.section .text.start, "ax"
+	.globl _start
+_start:
+	/* Belt-and-braces: no traps expected, but if one fires, land on a
+	 * tight loop at a known address rather than executing garbage. */
+	la	t0, _trap
+	csrw	mtvec, t0
+
+	la	sp, __stack_top
+
+	/* Clear .bss */
+	la	a0, __bss_start
+	la	a1, __bss_end
+1:	bgeu	a0, a1, 2f
+	sw	zero, 0(a0)
+	addi	a0, a0, 4
+	j	1b
+
+2:	call	main
+	/* main never returns; if it does, spin. */
+_trap:
+3:	j	3b