sim: RGA + NPU models (P3) — completes the RGA/RISC-V/NPU simulator requirement

- npu.rs: /proc/rknpu/load model (present-at-load% vs absent) mirroring sysmon's
  parse; 100% coverage.
- rga.rs: recording improcess() fake — logs dispatched blits + programmable
  IM_STATUS to drive the CPU-fallback path; the blit pixels aren't modelled, the
  dispatch logic is; 100% coverage.
- lib.rs re-exports NpuSim / RgaSim / Blit / Surface / Rect / ImStatus.
37 sim tests green; RISC-V (hpmcu) + RGA + NPU all simulated per future-features-2 §SDK.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf

sim/src/lib.rs

@@ -3,20 +3,26 @@
 //! Lets driver and supervisor logic run and be tested on the host, with no panel,
 //! by modelling the RV1106 hardware the vendor SDK cannot: the register/SRAM bus
 //! ([`membus`]), the RISC-V HPMCU watchdog coprocessor ([`hpmcu`]), the CRU reset
-//! ladder ([`cru`]), and the RS-485 device end ([`modbus`]) — and, as they land,
-//! the RGA blitter and the NPU.
+//! ladder ([`cru`]), the RS-485 device end ([`modbus`]), the **RGA** 2D blitter
+//! ([`rga`], a recording `improcess` fake), and the **NPU** load surface ([`npu`],
+//! the `/proc/rknpu/load` model).
 //!
 //! Design: one [`membus::MemBus`] seam, two backends. On the host, [`membus::SimBus`]
 //! is an in-memory word map; on the device, flared's `devmem.rs` implements the same
 //! trait over `/dev/mem`, so the same code runs against either. See the repo README.
-//! (The [`modbus`] slave rides a byte-stream seam, not the register bus.)
+//! (The [`modbus`] slave rides a byte-stream seam and [`rga`] its own call seam, not
+//! the register bus.)
 
 pub mod cru;
 pub mod hpmcu;
 pub mod membus;
 pub mod modbus;
+pub mod npu;
+pub mod rga;
 
 pub use cru::{BootMode, CruSim, ResetCause};
 pub use hpmcu::HpmcuSim;
 pub use membus::{MemBus, SimBus};
 pub use modbus::ModbusSlave;
+pub use npu::NpuSim;
+pub use rga::{Blit, ImStatus, Rect, RgaSim, Surface};