From d50934d048b3a222a65f7279cfb9c636cbbd3015 Mon Sep 17 00:00:00 2001 From: BFE Engineering Date: Mon, 24 Aug 2026 18:39:38 -0600 Subject: [PATCH] =?UTF-8?q?kernel:=20M2=20earlycon=20build=20=E2=80=94=20f?= =?UTF-8?q?ull=206.18=20zImage=20+=20minimal=20RV1106=20board=20DT?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit M1 is complete (clk + pinctrl + mach compile clean); this reaches M2's build milestone. multi_v7_defconfig + configs/m2-earlycon.fragment builds an 11.8 MB zImage with clk-rv1106.o and pinctrl-rockchip.o (our rv1106 data) compiled into the full tree — no rv1106 warnings. dts/rv1106-warden-m2.dts (CPU, GIC-400, arch timer, 256 MiB RAM, GRF, the CRU, uart2 as snps,dw-apb-uart) compiles clean at W=1 with earlycon=uart8250,mmio32,0xff4c0000. Reproducible via build-m2.sh. Boot is the next step and is on-hardware/attended: package zImage + dtb, load on a bench unit with a recovery net, watch for the earlycon "it's alive". PORT-VERIFY before trusting a boot: DDR size/base, the CPU clock mux, console baud. Co-Authored-By: Claude Opus 4.8 Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf --- kernel/rv1106-enablement/PORT-STATUS.md | 45 +++++-- kernel/rv1106-enablement/build-m2.sh | 41 ++++++ .../configs/m2-earlycon.fragment | 25 ++++ .../dts/rv1106-warden-m2.dts | 117 ++++++++++++++++++ 4 files changed, 219 insertions(+), 9 deletions(-) create mode 100755 kernel/rv1106-enablement/build-m2.sh create mode 100644 kernel/rv1106-enablement/configs/m2-earlycon.fragment create mode 100644 kernel/rv1106-enablement/dts/rv1106-warden-m2.dts diff --git a/kernel/rv1106-enablement/PORT-STATUS.md b/kernel/rv1106-enablement/PORT-STATUS.md index 62e018e..718ae1f 100644 --- a/kernel/rv1106-enablement/PORT-STATUS.md +++ b/kernel/rv1106-enablement/PORT-STATUS.md @@ -48,11 +48,36 @@ RV1106:` in the 3 pull functions + the RK3568 drive-strength group; `rv1106_pin_ - **Still PORT-VERIFY:** GPIO4 bank pin-count (`pin_banks` says 24, DT `gpio-ranges` says 32) — carried from vendor unchanged; needs TRM/hardware. -## M1 — mach + defconfig: NEXT -Per the breadth survey's integration order: mach is a ~2-line DT-compat add to `rockchip.c` -(do NOT recreate the dropped `CPU_RV1106` symbol); then the minimal M2 defconfig; then the DT -(SoC nodes transplant + board-specific PORT-VERIFY: console UART, boot media, panel timings); -then the first full kernel build toward an earlycon boot. +## M1 — mach: ✅ DONE +`mach-rockchip` RV1106/RV1103 SoC recognition added as a DT-compat entry (no +`CPU_RV1106` symbol recreated). Captured as `mach/0001-rv1106-soc-recognition.patch`. +**M1 is complete: clk + pinctrl + mach all compile clean on 6.18.** + +## M2 — earlycon build: ✅ DONE (boot pending hardware) +The first full kernel build with our SoC drivers, 2026-08-24: +- **`multi_v7_defconfig` + `configs/m2-earlycon.fragment` builds an 11.8 MB zImage** + with `clk-rv1106.o` (85732 B) and `pinctrl-rockchip.o` (173688 B, our rv1106 data) + compiled *into the full tree* — no rv1106 warnings/errors. Reproducible via + `build-m2.sh`. +- **`dts/rv1106-warden-m2.dts` → `rv1106-warden-m2.dtb` compiles clean** (W=1, no dtc + warnings). A deliberately minimal DT — CPU (cortex-a7), GIC-400, arch timer, 256 MiB + RAM, GRF, the CRU (our clk-rv1106), and uart2 (`snps,dw-apb-uart`, the console) — + with `earlycon=uart8250,mmio32,0xff4c0000` so the first print reuses the loader's + divisor before any clock/pinctrl probe. + +**Still PORT-VERIFY before a boot is trusted:** memory size/base (256 MiB @ 0x0 assumed +— the loader usually patches this); the CPU clock mux in clk-rv1106 (§M1 item 4); the +console baud (1.5M assumed). A wrong DDR/clock value silently hangs before or just after +earlycon. + +## M2 — boot: NEXT (on hardware) +Package `zImage` + `rv1106-warden-m2.dtb` into a boot image and load on a bench unit +(c8a3 / w7159, both with a proven recovery net), watching the debug UART — or the +coprocessor USB console (R5) — for the earlycon "it's alive". A hang is expected to be +one of the PORT-VERIFY values above; iterate with recovery ready. This is an attended +step (brick-adjacent), not an unattended one. + +Then M3: `dw_mmc` DT + rootfs on our Buildroot userspace. ## Upstream tracking (decision 2026-08-23) Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream @@ -69,10 +94,12 @@ on-hardware validation — which waits on c8a3's recovery and, ultimately, caref ## Layout ``` -clk/ - clk-rv1106.c the ported driver (WIP, compiles to :427) - rv1106-cru.h the clock-id dt-bindings header (staged) - 0001-rv1106-clk-framework-hooks.wip.patch Makefile/Kconfig/clk.h deltas vs vanilla 6.18 +clk/ clk-rv1106.c + rv1106-cru.h + framework-hooks patch (M1) +pinctrl/ 0001-rv1106-pinctrl.patch (M1) +mach/ 0001-rv1106-soc-recognition.patch (M1) +dts/ rv1106-warden-m2.dts minimal earlycon board DT (M2) +configs/ m2-earlycon.fragment defconfig delta over multi_v7 (M2) +build-m2.sh reproducible M2 build (zImage + dtb) ``` The full ported tree lives in `flare-edge/research/linux-6.18.46/` (scratch); this dir is the durable, reviewable capture, to become a proper patch series as milestones land. diff --git a/kernel/rv1106-enablement/build-m2.sh b/kernel/rv1106-enablement/build-m2.sh new file mode 100755 index 0000000..9a651dd --- /dev/null +++ b/kernel/rv1106-enablement/build-m2.sh @@ -0,0 +1,41 @@ +#!/usr/bin/env bash +# build-m2.sh — reproducible M2 (earlycon) build of the RV1106 → 6.18 forward-port. +# +# Produces: a zImage with our ported SoC drivers, and rv1106-warden-m2.dtb. +# Boot is a separate on-hardware step (see PORT-STATUS.md "M2 boot"). +# +# Usage: KTREE=/path/to/linux-6.18.46 SDK_TC=/path/to/toolchain/bin ./build-m2.sh +# Defaults match this workspace. +set -euo pipefail + +FE="${FE:-}" +KTREE="${KTREE:-$FE/research/linux-6.18.46}" +SDK_TC="${SDK_TC:-$FE/sdk/tools/linux/toolchain/arm-rockchip830-linux-uclibcgnueabihf/bin}" +HERE="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" + +# The SDK toolchain bakes absolute paths and needs `python` (not python3) + a +# space-free PATH (see the flare-edge-sdk-path-compat note). +export PATH="$SDK_TC:/usr/bin:/bin" +export ARCH=arm +export CROSS_COMPILE=arm-rockchip830-linux-uclibcgnueabihf- + +[ -d "$KTREE" ] || { echo "kernel tree not found: $KTREE" >&2; exit 1; } +command -v python >/dev/null || { echo "need 'python' on PATH (SDK quirk)" >&2; exit 1; } + +# Stage our board DT into the tree if it drifted from the capture. +install -m664 "$HERE/dts/rv1106-warden-m2.dts" \ + "$KTREE/arch/arm/boot/dts/rockchip/rv1106-warden-m2.dts" +grep -q 'rv1106-warden-m2.dtb' "$KTREE/arch/arm/boot/dts/rockchip/Makefile" \ + || sed -i 's/\trk3288-vyasa.dtb/\trk3288-vyasa.dtb \\\n\trv1106-warden-m2.dtb/' \ + "$KTREE/arch/arm/boot/dts/rockchip/Makefile" + +cd "$KTREE" +make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE" multi_v7_defconfig +./scripts/kconfig/merge_config.sh -m .config "$HERE/configs/m2-earlycon.fragment" +make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE" olddefconfig +make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE" -j"$(nproc)" zImage +make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE" rockchip/rv1106-warden-m2.dtb + +echo +echo "== M2 build OK ==" +ls -la arch/arm/boot/zImage arch/arm/boot/dts/rockchip/rv1106-warden-m2.dtb diff --git a/kernel/rv1106-enablement/configs/m2-earlycon.fragment b/kernel/rv1106-enablement/configs/m2-earlycon.fragment new file mode 100644 index 0000000..bd23b57 --- /dev/null +++ b/kernel/rv1106-enablement/configs/m2-earlycon.fragment @@ -0,0 +1,25 @@ +# M2 earlycon config fragment for the RV1106 → Linux 6.18 forward-port. +# +# Base: multi_v7_defconfig (PORT-STATUS confirms it configures and CLK_RV1106 +# wires in cleanly). Apply this fragment on top, then `make olddefconfig`: +# +# make ARCH=arm CROSS_COMPILE=arm-rockchip830-linux-uclibcgnueabihf- multi_v7_defconfig +# ./scripts/kconfig/merge_config.sh -m .config kernel/.../configs/m2-earlycon.fragment +# make ARCH=arm CROSS_COMPILE=... olddefconfig zImage +# +# This builds an 11.8 MB zImage with our ported SoC drivers compiled in +# (clk-rv1106.o, pinctrl-rockchip.o with the rv1106 data) — verified 2026-08-24. + +# --- our ported RV1106 SoC drivers --- +CONFIG_ARCH_ROCKCHIP=y +CONFIG_CLK_RV1106=y +CONFIG_PINCTRL_ROCKCHIP=y + +# --- console: mainline 8250_dw drives uart2 (snps,dw-apb-uart) --- +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y + +# --- earlycon: the "it's alive" print, before clk/pinctrl probe --- +CONFIG_SERIAL_EARLYCON=y diff --git a/kernel/rv1106-enablement/dts/rv1106-warden-m2.dts b/kernel/rv1106-enablement/dts/rv1106-warden-m2.dts new file mode 100644 index 0000000..91413f0 --- /dev/null +++ b/kernel/rv1106-enablement/dts/rv1106-warden-m2.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal RV1106 devicetree for the WardenOS 86-Panel — M2 "earlycon" bring-up + * of the self-built Linux 6.18 forward-port (warden-sdk kernel/docs/bringup.md). + * + * Deliberately NOT the full vendor rv1106.dtsi: just the core needed to reach + * "it's alive" on the debug UART — CPU, GIC, arch timer, RAM, the CRU (our + * ported clk-rv1106), GRF, and uart2 (the console, driven by mainline 8250_dw). + * earlycon writes uart2's MMIO directly at the bootloader's divisor, so it prints + * before the clock/pinctrl drivers probe; the real ttyS console then needs the + * CRU to hand out SCLK_UART2, which is exactly what this validates on hardware. + * + * PORT-VERIFY (must be checked against the TRM / on hardware before trusting a + * boot — a wrong value here silently hangs the board): + * - memory size/base (256 MiB @ 0x0 assumed for the 86-Panel; the loader + * usually patches this — confirm against the real DDR init); + * - uart2 is the console at 0xff4c0000 (matches the vendor ttyFIQ0 base); + * - CRU needs no assigned-clocks here (PLLs keep their loader rates) — fine for + * earlycon/console, revisit for the full clock tree. + */ +/dts-v1/; + +#include +#include +#include + +/ { + model = "WardenOS 86-Panel (RV1106) — M2 earlycon bring-up"; + compatible = "rockchip,rv1106"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + /* + * earlycon with no baud = reuse the divisor the bootloader left in + * uart2, so the first prints work regardless of our clock tree. The + * ttyS console rate (1.5M) is PORT-VERIFY against the board. + */ + bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyS2,1500000n8 earlyprintk rootwait"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MiB — PORT-VERIFY */ + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&cru ARMCLK>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + clock-frequency = <24000000>; + }; + + gic: interrupt-controller@ff1f0000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0xff1f1000 0x1000>, + <0xff1f2000 0x2000>, + <0xff1f4000 0x2000>, + <0xff1f6000 0x2000>; + interrupts = ; + }; + + grf: syscon@ff000000 { + compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd"; + reg = <0xff000000 0x68000>; + }; + + cru: clock-controller@ff3a0000 { + compatible = "rockchip,rv1106-cru"; + reg = <0xff3a0000 0x20000>; + rockchip,grf = <&grf>; + clocks = <&xin24m>; + clock-names = "xin24m"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + uart2: serial@ff4c0000 { + compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; + reg = <0xff4c0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + status = "okay"; + }; +};