Models the RV1106 reset ladder + boot-mode register on the MemBus seam, so
flared's devmem::hard_reset ladder and the boot-mode -> MaskRom recovery
maneuver are testable entirely on the host. Bakes in the two hardware facts
that cost real bench time as regression tests:
- the CRU global-reset register is 0xff3b0c08/0xfdb9; the magic at the wrong
offset 0xff3a0614 (from other Rockchip SoCs) is a SILENT NO-OP here;
- the boot-mode register 0xff020200 survives a warm reset (the mechanism that
makes "set MaskRom, then reset" drop the SoC into BootROM download), and a
power-on reset clears it.
6 tests (both rungs, pet, the wrong-offset no-op, MaskRom-survives-warm-reset,
POR-clears-request); the sim crate is 14/14 green.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
2-line DT-compat add to rockchip_board_dt_compat[] (rv1103 + rv1106), per the
breadth survey. Did NOT recreate the dropped CPU_RV1106 symbol (mainline IDs the
SoC purely via DT compat at runtime). clk + pinctrl + mach = the 3 core compile
components; DT + defconfig + full build remain for M2 (console boot).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
M1 pinctrl ported from vendor 5.10 (effort S, no API drift): enum, DRV/PULL/SMT
macros + 3 calc fns, case RV1106 in the 3 pull fns + RK3568 drive group, pin_banks
+ pin_ctrl, of_device_id (dropped CPU_RV1106 guard). pinctrl-rockchip.o 173KB, no
errors. iomux DRV/PULL/SMT offsets cross-validated against the upstream Simon Glass
v3 patch (match with the 0x10000 per-bank IOC base) -> the boot-critical iomux
PORT-VERIFY is retired via a 3rd independent source, no hardware. Upstream tracked
as a correctness oracle (doesn't apply to 6.18 cleanly; unmerged).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Per [maintainer]: forward-port the RV1106 SoC enablement from the vendor 5.10 tree to
6.18 LTS ourselves (no plan44), on our Buildroot. Verified mainline has ZERO
RV1106 support, so this is a whole-BSP port. docs/bringup.md = the console-first
milestone plan + method (sibling-delta from rv1126/rv1108, which exist in both
trees). M1 (clk driver) underway: gcc-8.3 builds 6.18; wired CLK_RV1106; ported
55 CRU macros + the panic_notifier header split + the armclk signature change
(flagged PORT-VERIFY for the CPU-mux, TRM-check needed). Captured in
rv1106-enablement/. Honest: first of ~120 files; multi-month effort.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Grounded in a full survey of the flare-edge firmware: catalogs every hardware
seam (register/MemBus, resource-path env-override, RGA compile-time), the tiered
MC/DC target (our code real MC/DC via the uboot-ab pattern; blobs fault-injection),
the target-config-lint class that the sim CANNOT cover (the 0x40000 brick), and
the ordered plan. Notes the flared<-warden-sim Cargo dep needs a repo remote
([maintainer] go-ahead).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
New from-scratch SDK for WardenOS (RV1106). First substance: the hardware
simulator's core — a MemBus register/SRAM seam (one trait, real /dev/mem backend
on device + in-memory SimBus on host) and a faithful port of the HPMCU watchdog
firmware (hpmcu/watchdog/main.c) as HpmcuSim, with 8 tests validating boot-grace
fire, heartbeat-timeout, disarm stand-down, and the flared arm-within-grace safety
property (no boot-loop) — all off-device, in a virtual clock, in <1ms.
This closes the gap the Explore map flagged: flared's devmem.rs/hpmcu.rs are the
only register-touching modules with zero tests. README lays out the SDK vision
(modern kernel, tiered driver MC/DC, proper RGA/HPMCU/NPU simulator, own repo).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
