Commit Graph
54 Commits
Author SHA1 Message Date
BFE EngineeringandClaude Opus 4.8 656b463039 kernel: clk-rv1106.c COMPILES CLEAN on 6.18 (M1 first driver ported)
Full clk port done: Kconfig/Makefile wired, 55 CRU macros, panic_notifier header
split, armclk signature adaptation, CLK_FRAC_DIVIDER_NO_LIMIT->0. clk-rv1106.o
(85KB) builds no-errors with gcc-8.3. Two PORT-VERIFY flags (CPU mux, UART frac
baud) for TRM/hardware validation. First RV1106 driver ported vendor-5.10->6.18.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
2026-08-23 10:50:24 -06:00
BFE EngineeringandClaude Opus 4.8 869fcebe6f kernel: start RV1106 -> Linux 6.18 forward-port (self-built, from vendor 5.10)
Per [maintainer]: forward-port the RV1106 SoC enablement from the vendor 5.10 tree to
6.18 LTS ourselves (no plan44), on our Buildroot. Verified mainline has ZERO
RV1106 support, so this is a whole-BSP port. docs/bringup.md = the console-first
milestone plan + method (sibling-delta from rv1126/rv1108, which exist in both
trees). M1 (clk driver) underway: gcc-8.3 builds 6.18; wired CLK_RV1106; ported
55 CRU macros + the panic_notifier header split + the armclk signature change
(flagged PORT-VERIFY for the CPU-mux, TRM-check needed). Captured in
rv1106-enablement/. Honest: first of ~120 files; multi-month effort.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
2026-08-23 10:32:33 -06:00
BFE EngineeringandClaude Opus 4.8 d4e1591517 docs: seam taxonomy + driver-hardening/MC-DC plan + sim roadmap
Grounded in a full survey of the flare-edge firmware: catalogs every hardware
seam (register/MemBus, resource-path env-override, RGA compile-time), the tiered
MC/DC target (our code real MC/DC via the uboot-ab pattern; blobs fault-injection),
the target-config-lint class that the sim CANNOT cover (the 0x40000 brick), and
the ordered plan. Notes the flared<-warden-sim Cargo dep needs a repo remote
([maintainer] go-ahead).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
2026-08-23 09:29:05 -06:00
BFE EngineeringandClaude Opus 4.8 c1331a582b warden-sdk: bootstrap repo + HPMCU (RISC-V) watchdog simulator
New from-scratch SDK for WardenOS (RV1106). First substance: the hardware
simulator's core — a MemBus register/SRAM seam (one trait, real /dev/mem backend
on device + in-memory SimBus on host) and a faithful port of the HPMCU watchdog
firmware (hpmcu/watchdog/main.c) as HpmcuSim, with 8 tests validating boot-grace
fire, heartbeat-timeout, disarm stand-down, and the flared arm-within-grace safety
property (no boot-loop) — all off-device, in a virtual clock, in <1ms.

This closes the gap the Explore map flagged: flared's devmem.rs/hpmcu.rs are the
only register-touching modules with zero tests. README lays out the SDK vision
(modern kernel, tiered driver MC/DC, proper RGA/HPMCU/NPU simulator, own repo).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
2026-08-23 09:23:37 -06:00