BFE EngineeringandClaude Opus 4.8
6fcfb80e5a
benches/sim_bench.rs (harness=false, zero deps): fixed-iteration ns/op timing for hpmcu_tick, cru_poll, modbus_read_holding, rga_improcess, membus_poke_peek. Human timings to stdout, one JSON trend line per bench to stderr for CI capture. New CI `bench` job smoke-runs them. Regression-vs-history gating is future work. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
79 lines
2.4 KiB
Rust
79 lines
2.4 KiB
Rust
//! Micro-benchmarks for the warden-sim hardware models.
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//!
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//! Dependency-free (`harness = false`): a fixed-iteration timing loop, so the sim
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//! crate keeps zero deps and CI can capture a stable ns/op number per model with no
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//! criterion tree to compile. Human-readable timings go to stdout; one JSON line per
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//! benchmark goes to stderr for CI trend capture (`bench: … ns_per_op …`).
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//!
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//! Run: `cargo bench` (or `cargo run --release --bench sim_bench`).
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use std::time::Instant;
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use warden_sim::{CruSim, HpmcuSim, MemBus, ModbusSlave, Rect, RgaSim, SimBus, Surface};
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fn bench<F: FnMut()>(name: &str, iters: u64, mut f: F) {
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for _ in 0..(iters / 10).max(1) {
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f(); // warm up
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}
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let t = Instant::now();
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for _ in 0..iters {
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f();
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}
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let ns = t.elapsed().as_nanos() as f64 / iters as f64;
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println!("{name:<24} {ns:>9.1} ns/op ({iters} iters)");
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eprintln!("{{\"bench\":\"{name}\",\"ns_per_op\":{ns:.1},\"iters\":{iters}}}");
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}
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fn main() {
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const N: u64 = 1_000_000;
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// HPMCU watchdog: one tick (mailbox poke + two peeks + state machine).
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{
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let mut h = HpmcuSim::new(SimBus::new(), 0, 0);
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let mut now = 0u64;
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bench("hpmcu_tick", N, || {
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now += 1;
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h.tick(now);
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});
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}
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// CRU reset ladder: one poll.
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{
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let mut c = CruSim::new(SimBus::new());
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let mut now = 0u64;
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bench("cru_poll", N, || {
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now += 1;
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let _ = c.poll(now);
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});
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}
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// Modbus RTU: a read-holding-registers request -> response round trip.
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{
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let mut s = ModbusSlave::new(1, 16, 16);
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s.set_holding(0, 0x1234);
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let req = warden_sim::modbus::request(1, &[0x03, 0x00, 0x00, 0x00, 0x04]);
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bench("modbus_read_holding", N, || {
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let _ = s.handle_frame(&req);
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});
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}
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// RGA: one improcess dispatch record (+ clear, so the log stays bounded).
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{
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let mut r = RgaSim::new();
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let sf = Surface { width: 720, height: 720, format: 0 };
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let rc = Rect { x: 0, y: 0, w: 720, h: 720 };
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bench("rga_improcess", N, || {
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let _ = r.improcess(sf, sf, rc, rc);
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r.clear();
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});
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}
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// MemBus: a poke + peek round trip (the /dev/mem seam's hot path).
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{
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let bus = SimBus::new();
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bench("membus_poke_peek", N, || {
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bus.poke32(0x100, 0xdead_beef);
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let _ = bus.peek32(0x100);
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});
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}
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}
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