BFE EngineeringandClaude Opus 4.8
6897c9f93e
Driver built into self-built 6.18 (=y): zImage 12.7MB + rv1106-warden.dtb build clean; System.map confirms aicbsp_sdio_driver, aicwf_sdio_driver, rwnx_cfg80211_ops linked with correct bsp->fdrv->btlpm initcall order (host nm/System.map — cross-nm/ar mis-list these, verify with System.map). Recipe captured (driver .c is vendor GPL source in the SDK, not duplicated): - kbuild/ — from-scratch in-tree Kconfig + Makefiles (bsp->fdrv->btlpm link order; tristate->default y; AIC_FW_PATH as a real Kconfig string symbol). - wifi-dt-block.dtsi — sdio_pwrseq (mmc-pwrseq-simple, reset gpio1 PA2) + &sdmmc (mmc@ffaa0000, supports-sdio, cap-sdio-irq, non-removable). - PORT-PROGRESS.md — full file->change log: ~30 timer/netdev renames, 7 cfg80211_ops signature deltas, link_id args, wakeup_source API rewrite, 49 bsp/fdrv symbol collisions renamed aicbsp_priv_*, rwnx_mesh restore. Firmware present on both oem_a+oem_b (/oem/usr/ko/aic8800dc_fw); on-hardware wlan0 verify next. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
41 lines
872 B
Devicetree
41 lines
872 B
Devicetree
/* --- M5: AIC8800DC wifi/BT power sequencing --- */
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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pinctrl-names = "default";
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reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
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};
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};
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/* --- console --- */
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&uart2 {
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status = "okay";
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};
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/* --- eMMC rootfs (M3) --- */
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&emmc {
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bus-width = <8>;
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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non-removable;
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status = "okay";
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};
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/* --- M5: AIC8800DC wifi/BT SDIO (on &sdmmc, mmc@ffaa0000 — NOT &sdio) --- */
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&sdmmc {
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max-frequency = <50000000>;
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bus-width = <4>;
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cap-sd-highspeed;
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cap-sdio-irq;
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keep-power-in-suspend;
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non-removable;
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rockchip,default-sample-phase = <90>;
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supports-sdio;
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mmc-pwrseq = <&sdio_pwrseq>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
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status = "okay";
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};
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/* --- batch 1: mainline peripherals (wire DT + config) --- */
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&uart1 {
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