BFE EngineeringandClaude Opus 4.8
749f73568a
RTC: ported the vendor rockchip,rv1106-rtc driver (rtc-rockchip.c) to 6.18 — one API delta (rtc_register_device -> devm_rtc_register_device). Verified on warden-c8a3: /dev/rtc0 registers and reads. tsadc thermal: ported the rv1106 data + rk_tsadcv9_initialize + the TSADCV9/VOGRF macros + code table from the vendor; adapted .chn_id[SENSOR_CPU] -> .chn_offset for 6.18. Verified: thermal_zone0 "soc-thermal" reads 39.8 C. i2s-tdm: rv1126 fallback compatible added (DAI builds; sound card needs the acodec port next). saradc still -22 (clk-rv1106 SARADC divider — deferred). Includes the NPU + RGA open-source port plans (research): rknpu kernel driver is a small port (RV1106 config already in the vendor driver; 4 dead-code headers need compat stubs) but no open userspace exists for this NPU gen; RGA = port the vendor char-dev rga3 driver (WardenOS's librga uses /dev/rga, not V4L2), + a cma pool + hrtimer_setup. All ports are open source (vendor C source / mainline siblings). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
63 lines
2.2 KiB
GLSL
63 lines
2.2 KiB
GLSL
/* --- rv1106 tsadc port (from vendor) --- */
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static const struct tsadc_table rv1106_code_table[] = {
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{0, MIN_TEMP},
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{363, MIN_TEMP},
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{396, -40000},
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{504, 25000},
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{605, 85000},
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{673, 125000},
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{758, MAX_TEMP},
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{TSADCV2_DATA_MASK, MAX_TEMP},
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};
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static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs,
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enum tshut_polarity tshut_polarity)
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{
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regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN);
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udelay(10);
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regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA);
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udelay(100);
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writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
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writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
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regs + TSADCV3_AUTO_PERIOD_HT);
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writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
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regs + TSADCV3_HIGHT_INT_DEBOUNCE);
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writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
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regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
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writel_relaxed(TSADCV9_AUTO_SRC, regs + TSADCV2_INT_PD);
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writel_relaxed(TSADCV9_PD_MODE, regs + TSADCV9_FLOW_CON);
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writel_relaxed(TSADCV9_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
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if (tshut_polarity == TSHUT_HIGH_ACTIVE)
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writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
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TSADCV2_AUTO_TSHUT_POLARITY_MASK,
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regs + TSADCV2_AUTO_CON);
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else
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writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
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regs + TSADCV2_AUTO_CON);
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writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | (TSADCV3_AUTO_Q_SEL_EN << 16),
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regs + TSADCV2_AUTO_CON);
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}
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static const struct rockchip_tsadc_chip rv1106_tsadc_data = {
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/* top, big_core0, big_core1, little_core, center, gpu, npu */
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.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
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.chn_num = 1, /* seven channels for tsadc */
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.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
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.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
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.tshut_temp = 95000,
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.initialize = rk_tsadcv9_initialize,
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.irq_ack = rk_tsadcv4_irq_ack,
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.control = rk_tsadcv4_control,
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.get_temp = rk_tsadcv4_get_temp,
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.set_alarm_temp = rk_tsadcv3_alarm_temp,
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.set_tshut_temp = rk_tsadcv3_tshut_temp,
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.set_tshut_mode = rk_tsadcv4_tshut_mode,
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.table = {
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.id = rv1106_code_table,
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.length = ARRAY_SIZE(rv1106_code_table),
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.data_mask = TSADCV2_DATA_MASK,
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.mode = ADC_INCREMENT,
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},
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};
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