Files
bfe-core1106-sdk/kernel/rv1106-enablement/mailbox/scr1-echo/link.lds
T
BFE EngineeringandClaude Opus 4.8 7e76553bd7 kernel/rv1106: HPMCU mailbox 100% VERIFIED + open NPU driver VERIFIED
MAILBOX (fully open A7<->RISC-V SCR1 round-trip, 5/5 exact echoes on c8a3):
- rockchip-mailbox.c: rv1106 has 1 shared IRQ, not 4/channel -> added
  rv1106_drv_data{num_chans=1} + compatible (rk3368 fallback assumed 4 -> probe
  failed 'IRQ index 1 not found').
- clk-rv1106.c: CLK_CORE_MCU (SCR1 core clock) marked CLK_IGNORE_UNUSED -
  6.18's clk_disable_unused() was switching off the coprocessor clock so a
  loaded firmware never ran (5.10 left it on).
- Open SCR1 echo firmware (scr1-echo/, 154B RV32IMC) + load/test scripts;
  A2B_INTEN on the MCU side + CMD-then-DAT (DAT=doorbell) order. Loaded via the
  proven hpmcu.rs SRAM path; do NOT kill warden-flared (dw-wdt). mailbox/VERIFIED.md.

NPU (open GPL rknpu 0.9.2 kernel driver on 6.18):
- DT fix: base npu node lacks interrupt-names, driver requests IRQ byname
  'npu_irq' -> probe bailed -ENXIO. Added interrupt-names='npu_irq'.
- Verified: [drm] Initialized rknpu 0.9.2 on minor 1; /dev/dri/card1;
  rknpu_version_test PASS (0.9.2 + hw version, full power/clock/reset path).
- Honest ceiling: open compute (regcmd compiler) is a from-scratch ~person-year
  RE project, no RV1106 prior art; ship the driver, no blob. npu/VERIFIED.md.

DRIVER-PARITY + CAPABILITIES-AUDIT updated; dts snapshot refreshed.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
2026-08-25 08:36:56 -06:00

44 lines
1.1 KiB
Plaintext

/*
* HPMCU watchdog supervisor — linked into the hpmcu_sram carve-out.
*
* The RV1106's 256K on-chip SRAM at 0xFF6C0000 is split by the kernel DT
* (rv1106.dtsi sram@ff6c0000) into rkisp_sram (0x0..0x3e000) and hpmcu_sram
* (0x3e000..0x40000, i.e. 0xFF6FE000..0xFF700000). We live entirely inside
* the 8K hpmcu region:
*
* 0xFF6FE000 +0x0000 .text/.rodata/.data/.bss (this script: 0x1C00)
* 0xFF6FFC00 +0x1C00 stack (grows down from 0xFF6FFF00)
* 0xFF6FFF00 +0x1F00 heartbeat mailbox (shared with Linux, see main.c)
*/
OUTPUT_ARCH(riscv)
ENTRY(_start)
MEMORY
{
SRAM (rwx) : ORIGIN = 0xFF6FE000, LENGTH = 0x1C00
}
SECTIONS
{
.text : {
*(.text.start)
*(.text*)
} > SRAM
.rodata : { *(.rodata*) *(.srodata*) } > SRAM
.data : { *(.data*) *(.sdata*) } > SRAM
.bss (NOLOAD) : {
. = ALIGN(4);
__bss_start = .;
*(.bss*) *(.sbss*) *(COMMON)
. = ALIGN(4);
__bss_end = .;
} > SRAM
/* Stack: from the mailbox floor down toward .bss. */
__stack_top = 0xFF6FFF00;
/DISCARD/ : { *(.eh_frame) *(.riscv.attributes) *(.comment) }
}