BFE EngineeringandClaude Opus 4.8
5aedb5e966
The saradc -22 was regulator_get_voltage on a dummy vref (no vref-supply in DT), not the clk divider. Added vcc_1v8 fixed 1.8V regulator + vref-supply (matching the vendor 86-panel). iio:device0 now reads both channels (in_voltage0_raw=1023, in_voltage1_raw=246) — the adc-keys path works. Five drivers verified this run: wifi, TRNG, OTP, GMAC, SARADC. adc/SARADC-FIX.md; DRIVER-PARITY updated. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
RV1106 6.18 devicetree
rv1106-warden.dts— our board DT.#includes the vendorrv1106.dtsi(the full SoC: pinctrl, gpio×5, dmac, cru+grf_cru, uart, emmc, i2c, saradc, watchdog, usb, vop, npu, rga, …), then enables only what the wall-HMI needs. No camera/ISP/CSI. Grows one driver batch at a time (see../DRIVER-PARITY.md).rv1106-warden-m2.dts— the earlier standalone minimal DT used to bring up M2/M3 before the full-SoC transplant; kept for reference.
Transplanting the vendor SoC DT onto 6.18 (recipe)
Copy into arch/arm/boot/dts/rockchip/ of the 6.18 tree:
rv1106.dtsi, rv1106-pinctrl.dtsi, rockchip-pinconf.dtsi. Copy the
vendor-only dt-bindings headers into include/dt-bindings/:
soc/rockchip-system-status.h, suspend/rockchip-rv1106.h,
display/media-bus-format.h, and overwrite soc/rockchip,boot-mode.h
with the vendor's (it has extra BOOT_CHARGING/UMS/PANIC/WATCHDOG constants the
DT uses). Then the two hardware deltas:
- Delete the
pscinode fromrv1106.dtsi. RV1106 has no secure monitor in our boot chain, soarm,psci-1.0+method="smc"makes the SMC call fault →Oops - bad mode→Attempted to kill the idle task. (Confirmed on c8a3.) - Enable the peripherals in the board DTS (
&uart2,&emmc, …).
Verified on warden-c8a3: pinctrl, gpio0–4, pl330 DMA, uart1/2/4, i2c3, dw-wdt all probe; full WardenOS userspace boots.