BFE EngineeringandClaude Opus 4.8
c7ba8781a4
GMAC ✅ eth0 Link Up 100Mbps/Full on c8a3: ported rv1106_ops into mainline dwmac-rk.c (VOGRF RMII mode/speed + integrated FEPHY powerup via CON0; mainline set_speed/powerup split; bandgap trim omitted — analog opt the PHY runs without). &gmac enabled; uses the internal ethernet-phy@2. gmac/PORT-DONE.md. OTP ✅ now reads real data (px30_otp_read): 5211 02fe 084d 5231 ('MR1' chip id), no timeout. rng-otp/PORT-DONE.md updated. Batch A + GMAC complete — TRNG, OTP, GMAC all verified on hardware. DRIVER-PARITY updated. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
RV1106 6.18 devicetree
rv1106-warden.dts— our board DT.#includes the vendorrv1106.dtsi(the full SoC: pinctrl, gpio×5, dmac, cru+grf_cru, uart, emmc, i2c, saradc, watchdog, usb, vop, npu, rga, …), then enables only what the wall-HMI needs. No camera/ISP/CSI. Grows one driver batch at a time (see../DRIVER-PARITY.md).rv1106-warden-m2.dts— the earlier standalone minimal DT used to bring up M2/M3 before the full-SoC transplant; kept for reference.
Transplanting the vendor SoC DT onto 6.18 (recipe)
Copy into arch/arm/boot/dts/rockchip/ of the 6.18 tree:
rv1106.dtsi, rv1106-pinctrl.dtsi, rockchip-pinconf.dtsi. Copy the
vendor-only dt-bindings headers into include/dt-bindings/:
soc/rockchip-system-status.h, suspend/rockchip-rv1106.h,
display/media-bus-format.h, and overwrite soc/rockchip,boot-mode.h
with the vendor's (it has extra BOOT_CHARGING/UMS/PANIC/WATCHDOG constants the
DT uses). Then the two hardware deltas:
- Delete the
pscinode fromrv1106.dtsi. RV1106 has no secure monitor in our boot chain, soarm,psci-1.0+method="smc"makes the SMC call fault →Oops - bad mode→Attempted to kill the idle task. (Confirmed on c8a3.) - Enable the peripherals in the board DTS (
&uart2,&emmc, …).
Verified on warden-c8a3: pinctrl, gpio0–4, pl330 DMA, uart1/2/4, i2c3, dw-wdt all probe; full WardenOS userspace boots.