BFE EngineeringandClaude Opus 4.8 6fcfb80e5a bench: dependency-free sim micro-benchmarks + CI bench job (P4) ...

benches/sim_bench.rs (harness=false, zero deps): fixed-iteration ns/op timing for
hpmcu_tick, cru_poll, modbus_read_holding, rga_improcess, membus_poke_peek. Human
timings to stdout, one JSON trend line per bench to stderr for CI capture. New CI
`bench` job smoke-runs them. Regression-vs-history gating is future work.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf

2026-08-25 14:15:22 -06:00

..

benches

bench: dependency-free sim micro-benchmarks + CI bench job (P4)

2026-08-25 14:15:22 -06:00

src

sim: RGA + NPU models (P3) — completes the RGA/RISC-V/NPU simulator requirement

2026-08-25 14:12:10 -06:00

Cargo.lock

ci: commit Cargo.lock files for reproducible --locked builds

2026-08-25 13:53:11 -06:00

Cargo.toml

bench: dependency-free sim micro-benchmarks + CI bench job (P4)

2026-08-25 14:15:22 -06:00