BFE EngineeringandClaude Opus 4.8
6fcfb80e5a
benches/sim_bench.rs (harness=false, zero deps): fixed-iteration ns/op timing for hpmcu_tick, cru_poll, modbus_read_holding, rga_improcess, membus_poke_peek. Human timings to stdout, one JSON trend line per bench to stderr for CI capture. New CI `bench` job smoke-runs them. Regression-vs-history gating is future work. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
20 lines
483 B
TOML
20 lines
483 B
TOML
[package]
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name = "warden-sim"
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version = "0.1.0"
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edition = "2021"
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description = "Host-side hardware simulator for WardenOS: register/SRAM bus, HPMCU (RISC-V) watchdog, RGA, NPU. Lets driver and supervisor logic run and be tested with no panel."
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license = "MIT OR Apache-2.0"
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[lib]
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name = "warden_sim"
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path = "src/lib.rs"
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[dependencies]
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[dev-dependencies]
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# Dependency-free micro-benchmarks (fixed-iteration timing, no criterion tree).
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[[bench]]
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name = "sim_bench"
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harness = false
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