BFE EngineeringandClaude Opus 4.8
85b0db7eee
- npu.rs: /proc/rknpu/load model (present-at-load% vs absent) mirroring sysmon's parse; 100% coverage. - rga.rs: recording improcess() fake — logs dispatched blits + programmable IM_STATUS to drive the CPU-fallback path; the blit pixels aren't modelled, the dispatch logic is; 100% coverage. - lib.rs re-exports NpuSim / RgaSim / Blit / Surface / Rect / ImStatus. 37 sim tests green; RISC-V (hpmcu) + RGA + NPU all simulated per future-features-2 §SDK. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
29 lines
1.2 KiB
Rust
29 lines
1.2 KiB
Rust
//! warden-sim — host-side hardware simulator for WardenOS.
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//!
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//! Lets driver and supervisor logic run and be tested on the host, with no panel,
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//! by modelling the RV1106 hardware the vendor SDK cannot: the register/SRAM bus
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//! ([`membus`]), the RISC-V HPMCU watchdog coprocessor ([`hpmcu`]), the CRU reset
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//! ladder ([`cru`]), the RS-485 device end ([`modbus`]), the **RGA** 2D blitter
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//! ([`rga`], a recording `improcess` fake), and the **NPU** load surface ([`npu`],
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//! the `/proc/rknpu/load` model).
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//!
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//! Design: one [`membus::MemBus`] seam, two backends. On the host, [`membus::SimBus`]
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//! is an in-memory word map; on the device, flared's `devmem.rs` implements the same
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//! trait over `/dev/mem`, so the same code runs against either. See the repo README.
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//! (The [`modbus`] slave rides a byte-stream seam and [`rga`] its own call seam, not
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//! the register bus.)
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pub mod cru;
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pub mod hpmcu;
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pub mod membus;
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pub mod modbus;
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pub mod npu;
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pub mod rga;
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pub use cru::{BootMode, CruSim, ResetCause};
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pub use hpmcu::HpmcuSim;
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pub use membus::{MemBus, SimBus};
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pub use modbus::ModbusSlave;
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pub use npu::NpuSim;
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pub use rga::{Blit, ImStatus, Rect, RgaSim, Surface};
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