kernel: M2 DONE — self-built 6.18 boots on real RV1106 hardware (warden-c8a3)
The Linux 6.18.46 forward-port boots on the panel through our ported drivers, verified on the serial console: earlycon, arch timer (BogoMIPS calibrated), our clk-rv1106 CRU, pinctrl, and the mainline 8250 bound to uart2 clocked by our CRU (ttyS2 16550A), then rootfs mount. Two DT fixes got it past "Starting kernel": - fdt placed high (load=0x08000000) so the bloated multi_v7 zImage (~20 MiB decompressed) stops overrunning the DTB at 0xc00000 (was: r2=0, "invalid dtb"). - added the rockchip,rv1106-grf-cru node (grf-clock-controller child of grf) so clk-rv1106's grf_ctx isn't NULL (was: panic in rockchip_clk_register_branches). Console pinned to 115200 (readable on the CP2102 bench adapter; prod uses 1.5M). The boot-image format and the A/B _b-slot safe-test method (which auto-reverted to _a on every failed attempt) are in docs/m2-boot-on-c8a3.md. M3 next: lean defconfig + dw_mmc DT + our Buildroot userspace rebuilt on 6.18. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
This commit is contained in:
BFE Engineering
co-authored by
Claude Opus 4.8
Claude Opus 4.8
parent
b21229c8aa
commit
f3087399f2
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# M2 boot bring-up on warden-c8a3 (live notes)
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Booting the self-built 6.18 kernel on real hardware (warden-c8a3), 2026-08-24.
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The build side (zImage + dtb) is in `../rv1106-enablement/`; this is the on-target
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half. **The safe-test framework and the boot-image format below are the reusable
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findings — they worked on the first hardware try.**
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## The safe test path (A/B slot _b, never touch _a)
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c8a3 is the XPS-connected Warden: eth0 `[bench-ip]` over USB-gadget ([bench-creds],
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dropbear — use `scp -O`, no sftp-server), plus the serial console on xps
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`/dev/ttyUSB2` @115200 and Zigbee power (`plug_cmd.py cycle`). It runs an A/B
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firmware (boot_a=mmcblk0p5 / boot_b=mmcblk0p6, 32 MiB each; rootfs_a/_b; AvbABData
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in `misc` sector 4 / byte 2048).
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The test never risks the working system:
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1. Back up `boot_b` (`dd .../by-name/boot_b -> /userdata/boot_b.bak`).
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2. Write the test `boot.img` to **boot_b only** — `_a` (the shipped WardenOS) is
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untouched.
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3. Flip AvbABData to a **one-shot _b**: `craft_ab.py 14 0 1 15 1 0 1` → A(prio14,
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tries0,ok1) B(prio15,tries1,ok0); write to `misc` sector 4. U-Boot's SPL then
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picks _b once, decrements tries→0, and boots it.
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4. If the test kernel fails/hangs, U-Boot auto-reverts to `_a` (SPL: "slot boot
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failed, resetting" → next boot `A/B-slot: _a, successful: 1`). A hung kernel
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just needs a Zigbee power-cycle; `_a` boots WardenOS back. **Zero manual
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recovery needed — verified across three failed attempts.**
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`earlycon=uart8250,mmio32,0xff4c0000` is confirmed correct: it is in the live
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5.10 cmdline, and U-Boot's own DDR probe reports `Adding bank: 0x0 - 0x10000000`
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(256 MiB) — so the M2 DT's memory node and earlycon are right.
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## The boot-image format (this was the whole fight)
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rockchip U-Boot (this build) needs a very specific `boot.img`, NOT a plain FIT:
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- **External-data FIT.** `mkimage -f its -E -p 0x800`. The FDT metadata stays tiny
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(totalsize ≈ 1536 B, matching boot_a); the kernel/fdt/resource **data is
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appended** after it. A normal embedded-data FIT (totalsize = whole image) is
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rejected with `FIT: No fit blob` / `No FIT image`.
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- **A `resource` (multi) sub-image is mandatory.** rockchip reads the DTB via the
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`RESC:` path from a resource image containing `rk-kernel.dtb` (+ logos), built
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with `resource_tool --pack`. Without it: `Failed to load DTB, ret=-19`.
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- **Sysmem sentinel load addresses.** fdt `load=0xffffff00`, kernel
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`load=entry=0xffffff01`; U-Boot's sysmem places them (it chose kernel@0x8000,
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fdt@0xc00000). Real low addresses collided → "No fit blob".
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- `CONFIG_FIT_SIGNATURE` is **off** in this U-Boot, so the image need not be
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signed. Template: `sdk/sysdrv/source/kernel/boot.its`; builder recipe:
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`sdk/project/scripts/mk-fitimage.sh` (`mkimage -E -p 0x800`).
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With the correct format, U-Boot loaded my kernel + my DTB and printed my DT model
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string (`Model: WardenOS 86-Panel (RV1106) — M2 earlycon bring-up`), then
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`Starting kernel ...`.
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## Result: ✅ M2 achieved — the 6.18 kernel boots on hardware
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Six attempts, each auto-recovering to `_a`, then a clean boot:
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```
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[0.000000] Linux version 6.18.46 … #2 SMP
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[0.000000] CPU: ARMv7 Processor [410fc075]
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[0.000000] OF: fdt: Machine model: WardenOS 86-Panel (RV1106) — M2 earlycon bring-up
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[0.000000] earlycon: uart8250 at MMIO32 0xff4c0000
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[0.000000] cma: Reserved 64 MiB at 0x0c000000
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[0.040693] Calibrating delay loop … 48.00 BogoMIPS ← arch timer up
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[0.343810] pinctrl core: initialized pinctrl subsystem
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[1.968703] ff4c0000.serial: ttyS2 … is a 16550A ← 8250 on our CRU clock
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```
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Two more bugs, found via the DEBUG_LL rebuild (`DEBUG_LL_UART_8250`, PHYS
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0xff4c0000, shift 2, 32-bit word + `earlyprintk` — the decompressor prints
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pre-MMU), then fixed:
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- **DTB overrun → `r2=0` / `invalid dtb`.** The multi_v7 zImage decompresses to
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~20 MiB from 0x8000, overrunning the DTB at 0xc00000, so the decompressor handed
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the kernel a null DTB pointer. Fix: place the fdt high — `load=0x08000000` in the
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FIT `.its` (see `boot5.its`). The real fix is a lean defconfig; multi_v7 is bloat.
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- **`grf_ctx` NULL deref in clk-rv1106.** `rockchip_clk_register_branches(grf_ctx,…)`
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crashed because the minimal DT had no `rockchip,rv1106-grf-cru` node to set
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`grf_ctx`. Fix: add the `grf-clock-controller` child to the grf syscon (now in
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`dts/rv1106-warden-m2.dts`).
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**Console baud gotcha:** `console=ttyS2,115200`. earlycon is readable at 115200
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(U-Boot leaves uart2 there), but the vendor's 1.5M console rate is garbage on the
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CP2102 bench adapter — so the M2 DT pins 115200 for readable bring-up; production
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overrides to 1.5M.
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## Next (M3)
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The kernel mounts the 5.10 rootfs_b but the userspace/modules are 5.10 (vermagic
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mismatch). M3: lean RV1106 defconfig, `dw_mmc`/`sdhci` DT (eMMC already probes —
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`MMC0: HS200`), and our Buildroot userspace rebuilt on 6.18.
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@@ -70,14 +70,36 @@ The first full kernel build with our SoC drivers, 2026-08-24:
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console baud (1.5M assumed). A wrong DDR/clock value silently hangs before or just after
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earlycon.
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## M2 — boot: NEXT (on hardware)
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Package `zImage` + `rv1106-warden-m2.dtb` into a boot image and load on a bench unit
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(c8a3 / w7159, both with a proven recovery net), watching the debug UART — or the
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coprocessor USB console (R5) — for the earlycon "it's alive". A hang is expected to be
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one of the PORT-VERIFY values above; iterate with recovery ready. This is an attended
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step (brick-adjacent), not an unattended one.
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## M2 — boot: ✅ DONE — "it's alive" on warden-c8a3 (2026-08-24)
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The self-built **Linux 6.18.46 boots on real RV1106 hardware**, through our ported
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drivers, verified over the serial console. It reaches earlycon, the arch timer
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(BogoMIPS calibrated), **our `clk-rv1106` CRU driver**, pinctrl, and the mainline
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8250 bound to uart2 **clocked by our CRU** (`ttyS2 … 16550A`), then hands off to the
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real console and mounts a rootfs. See `../docs/m2-boot-on-c8a3.md` for the method
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(the A/B `_b`-slot safe-test framework worked first try) and the boot-image format
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(external-data FIT + resource, `mkimage -E -p 0x800`).
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Then M3: `dw_mmc` DT + rootfs on our Buildroot userspace.
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Three bring-up bugs were found and fixed on hardware, all captured in the DT:
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1. **boot.img format** — rockchip U-Boot needs the external-data FIT + a `resource`
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(multi) sub-image with `rk-kernel.dtb`, else `No fit blob` / `Failed to load DTB`.
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2. **DTB overrun** — the bloated multi_v7 zImage decompresses to ~20 MiB and overran
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the DTB at 0xc00000, so the kernel got `r2=0` (`invalid dtb`). Fix: place the fdt
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high (`load=0x08000000`). A lean RV1106 defconfig would also fix this and is the
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right long-term move.
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3. **grf-cru NULL deref** — `clk-rv1106` registers a second branch set against a GRF
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clock-controller (`grf_ctx`), set only by a `rockchip,rv1106-grf-cru` node. The
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minimal DT omitted it → `grf_ctx` NULL → panic in `rockchip_clk_register_branches`.
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Fix: add the `grf-clock-controller` child to the grf syscon.
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**clk-rv1106 PORT-VERIFY (armclk mux, PLL rates) is now partially retired**: the CRU
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comes up far enough to clock the UART and the arch timer on hardware. A wrong CPU
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mux/PLL would show later (cpufreq / peripheral rates), still to be checked.
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## M3 — rootfs boot: NEXT
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The M2 kernel mounts the 5.10 WardenOS rootfs_b but the userspace/module vermagic
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mismatches (5.10 `.ko` won't load on 6.18). M3 = a lean RV1106 defconfig (drop
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multi_v7), `dw_mmc`/`sdhci` DT wired to our CRU (eMMC already probes — `MMC0: HS200`),
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and our Buildroot userspace rebuilt against 6.18. Then M4 display, M5 wifi, M6 rest.
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## Upstream tracking (decision 2026-08-23)
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Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream
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@@ -36,13 +36,14 @@
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};
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chosen {
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stdout-path = "serial2:1500000n8";
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stdout-path = "serial2:115200n8";
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/*
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* earlycon with no baud = reuse the divisor the bootloader left in
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* uart2, so the first prints work regardless of our clock tree. The
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* ttyS console rate (1.5M) is PORT-VERIFY against the board.
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* uart2, so the first prints work regardless of our clock tree. The ttyS console is
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* pinned to 115200 to stay readable on the CP2102 bench adapter;
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* production WardenOS uses 1.5M.
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*/
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bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyS2,1500000n8 earlyprintk rootwait";
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bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyS2,115200n8 earlyprintk rootwait";
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};
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memory@0 {
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@@ -91,6 +92,14 @@
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grf: syscon@ff000000 {
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compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd";
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reg = <0xff000000 0x68000>;
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/* The CRU's clk-rv1106 registers a second branch set against this
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* GRF clock-controller (grf_ctx); without the node grf_ctx is NULL
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* and of_clk_init NULL-derefs in rockchip_clk_register_branches. */
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grf_cru: grf-clock-controller {
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compatible = "rockchip,rv1106-grf-cru";
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#clock-cells = <1>;
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};
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};
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cru: clock-controller@ff3a0000 {
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