 BFE EngineeringandClaude Opus 4.8
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85b0db7eee
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sim: RGA + NPU models (P3) — completes the RGA/RISC-V/NPU simulator requirement
- npu.rs: /proc/rknpu/load model (present-at-load% vs absent) mirroring sysmon's
parse; 100% coverage.
- rga.rs: recording improcess() fake — logs dispatched blits + programmable
IM_STATUS to drive the CPU-fallback path; the blit pixels aren't modelled, the
dispatch logic is; 100% coverage.
- lib.rs re-exports NpuSim / RgaSim / Blit / Surface / Rect / ImStatus.
37 sim tests green; RISC-V (hpmcu) + RGA + NPU all simulated per future-features-2 §SDK.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
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2026-08-25 14:12:10 -06:00 |
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