MAILBOX (fully open A7<->RISC-V SCR1 round-trip, 5/5 exact echoes on c8a3):
- rockchip-mailbox.c: rv1106 has 1 shared IRQ, not 4/channel -> added
rv1106_drv_data{num_chans=1} + compatible (rk3368 fallback assumed 4 -> probe
failed 'IRQ index 1 not found').
- clk-rv1106.c: CLK_CORE_MCU (SCR1 core clock) marked CLK_IGNORE_UNUSED -
6.18's clk_disable_unused() was switching off the coprocessor clock so a
loaded firmware never ran (5.10 left it on).
- Open SCR1 echo firmware (scr1-echo/, 154B RV32IMC) + load/test scripts;
A2B_INTEN on the MCU side + CMD-then-DAT (DAT=doorbell) order. Loaded via the
proven hpmcu.rs SRAM path; do NOT kill warden-flared (dw-wdt). mailbox/VERIFIED.md.
NPU (open GPL rknpu 0.9.2 kernel driver on 6.18):
- DT fix: base npu node lacks interrupt-names, driver requests IRQ byname
'npu_irq' -> probe bailed -ENXIO. Added interrupt-names='npu_irq'.
- Verified: [drm] Initialized rknpu 0.9.2 on minor 1; /dev/dri/card1;
rknpu_version_test PASS (0.9.2 + hw version, full power/clock/reset path).
- Honest ceiling: open compute (regcmd compiler) is a from-scratch ~person-year
RE project, no RV1106 prior art; ship the driver, no blob. npu/VERIFIED.md.
DRIVER-PARITY + CAPABILITIES-AUDIT updated; dts snapshot refreshed.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Six drivers verified on hardware this run (wifi, TRNG, OTP, GMAC, SARADC,
audio). Final honest ledger: mailbox (fallback-binds, no client), crypto-v3
(CPU crypto covers), NPU (no open userspace), pvtm (DVFS-only) all deferred
with reasons — no unexplored capability gap. Morning bench tasks documented
(display connector, audible audio, wifi boot-time auto-load).
OVERNIGHT-RESULTS.md added.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Ported rv1106_codec.c (acodec) + rk_dsm.c (built, dsm disabled — panel uses
acodec) into 6.18 (6 ASoC API-delta fixes: gpiod, volsw unify, DAIFMT CBC/CBP
rename, remove->void, header swaps). simple-audio-card 'rv1106-acodec'.
Fixed the subagent's gap: cpu DAI SND_SOC_ROCKCHIP_I2S_TDM was left =m (module,
never loaded on bare _b boot) so the card stuck in 'asoc-simple-card: parse
error' deferred probe. Set it + SND_SOC_ROCKCHIP =y.
✅ VERIFIED on c8a3: /proc/asound/cards shows rv1106-acodec; aplay -l shows
card 0 device 0 ffae0000.i2s-rv1106-hifi; /dev/snd has pcmC0D0p + pcmC0D0c.
Audible speaker test deferred to the bench (with display).
Six drivers verified this run: wifi, TRNG, OTP, GMAC, SARADC, audio.
audio/PORT-PROGRESS.md; DRIVER-PARITY updated; dts snapshot refreshed.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
The saradc -22 was regulator_get_voltage on a dummy vref (no vref-supply in
DT), not the clk divider. Added vcc_1v8 fixed 1.8V regulator + vref-supply
(matching the vendor 86-panel). iio:device0 now reads both channels
(in_voltage0_raw=1023, in_voltage1_raw=246) — the adc-keys path works.
Five drivers verified this run: wifi, TRNG, OTP, GMAC, SARADC.
adc/SARADC-FIX.md; DRIVER-PARITY updated.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
GMAC ✅ eth0 Link Up 100Mbps/Full on c8a3: ported rv1106_ops into mainline
dwmac-rk.c (VOGRF RMII mode/speed + integrated FEPHY powerup via CON0;
mainline set_speed/powerup split; bandgap trim omitted — analog opt the PHY
runs without). &gmac enabled; uses the internal ethernet-phy@2. gmac/PORT-DONE.md.
OTP ✅ now reads real data (px30_otp_read): 5211 02fe 084d 5231 ('MR1' chip id),
no timeout. rng-otp/PORT-DONE.md updated.
Batch A + GMAC complete — TRNG, OTP, GMAC all verified on hardware.
DRIVER-PARITY updated.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
On-hardware proof (self-built 6.18.46, _b slot): aic8800 modules load,
download firmware, wlan0 up ([device-mac]), iw scan finds real APs
incl. SSID BlueFlare @ -43dBm. RF path fully functional. See
wifi/VERIFIED-on-c8a3.md.
Two changes from the initial built-in attempt:
- Built-in =y DEADLOCKS: aicbsp_init's eager SDIO bring-up (device_initcall,
sequential) blocks the dw_mmc controller probe that would enumerate the
card it waits for (aicsdio.c:597 2s down_timeout -> unregister). Converted
to modules (=m): AIC_WLAN_SUPPORT bool->tristate; loaded late, after the
mmc-pwrseq enumerates the card — the vendor-proven flow.
- Restored fdrv's own md5.o (each .ko needs its own MD5; bsp doesn't export
it). Refreshed kbuild snapshot accordingly.
Kernel-size fix (CONFIG_KERNEL_GZIP -> XZ): the wifi kernel's 12.12MB gzip
zImage overran U-Boot's DTB-at-0xc00000 load boundary (Sysmem Error, FLARE-AB
fell back to _a). XZ -> 8.15MB, ~4MB headroom; also correct for a firmware
kernel. Uncompressed Image ~30MB but the ARM decompressor relocates the FDT
at runtime, so only the U-Boot load-time overlap mattered.
DRIVER-PARITY: wifi ✅ M5; BT 🔨 (module built, HCI not yet exercised).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Capabilities audit — classify every RV1106 SoC block against a 6.18 driver:
GMAC (wired eth, enabled on-board), crypto-v3, trngv1 (hw RNG), OTP, mailbox,
NPU, audio codec/DSM, pvtm still to port; camera/ISP + SPI are N/A (no HW).
Provenance ledger — per [maintainer]'s openness directive extended to already-ported
drivers: every ported driver is GPL-2.0 kernel source (vendor-src or
mainline-sibling); the only binary in the whole path is on-device wifi-chip
firmware, which by construction cannot be host source. No vendor binary is
loaded into our kernel.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
RTC: ported the vendor rockchip,rv1106-rtc driver (rtc-rockchip.c) to 6.18 — one
API delta (rtc_register_device -> devm_rtc_register_device). Verified on
warden-c8a3: /dev/rtc0 registers and reads.
tsadc thermal: ported the rv1106 data + rk_tsadcv9_initialize + the TSADCV9/VOGRF
macros + code table from the vendor; adapted .chn_id[SENSOR_CPU] -> .chn_offset
for 6.18. Verified: thermal_zone0 "soc-thermal" reads 39.8 C.
i2s-tdm: rv1126 fallback compatible added (DAI builds; sound card needs the acodec
port next). saradc still -22 (clk-rv1106 SARADC divider — deferred).
Includes the NPU + RGA open-source port plans (research): rknpu kernel driver is a
small port (RV1106 config already in the vendor driver; 4 dead-code headers need
compat stubs) but no open userspace exists for this NPU gen; RGA = port the vendor
char-dev rga3 driver (WardenOS's librga uses /dev/rga, not V4L2), + a cma pool +
hrtimer_setup. All ports are open source (vendor C source / mainline siblings).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
The brief: port/enable every remaining RV1106 hardware capability on 6.18,
open-source-first (source we own + can harden, never blobs), new drivers if
needed, zero capabilities left on the table. Priority: AIC8800 wifi/BT, RGA,
rknpu, RTC, tsadc, i2s, saradc-fix, eth0-gadget, then a full capabilities audit.
Display deferred to tomorrow (needs eyes on the panel). Pipelined: research
subagents ∥ port/build/verify on c8a3; krecover-hardened for resilience.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
usb2phy: ported the RV1106 inno-usb2 phy config to 6.18 (rv1106_usb2phy_cfg;
fields map 1:1 except utmi_iddig->utmi_id and chg_mode->opmode; 5.10-only
iddig_output/en/bvalid_grf_sel dropped; phy_tuning left off, guarded so safe).
With PHY_ROCKCHIP_INNO_USB2=y + the u2phy/usbdrd/dwc3 DT enabled, verified on
warden-c8a3: the DWC3 comes up as xhci-hcd @ 0xffb00000 — USB host works. eth0
gadget just needs dr_mode=peripheral.
saradc: added rv1106_saradc_data (2-ch v2, matches the vendor) + the native
compatible. Driver now matches; probe still returns -22 (a clk-rate/setup detail,
not the data) — TODO.
Also captured: the growing board dts (USB nodes), the port fragments under usb/
and adc/. DRIVER-PARITY.md updated: ~14 drivers now at parity on 6.18.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
The RV1106 VOP is the RV-series "lite" VOP (rockchip,rv1106-vop, VOP_VERSION 2.0xc),
mainline's VOP1 driver. Its sibling rv1126 is already in 6.18, so rv1106_vop reuses
rv1126's register sub-structs + VOP_FEATURE_INTERNAL_RGB + the smaller raster.
Verified on warden-c8a3: with the driver delta + DT (vop enabled with named
"ahb"/"dclk" resets, vop_out repointed to a panel-dpi 720x720 node, pwm-backlight
on pwm1), the VOP BINDS and DRM initialises (/dev/dri/card0), and the PWM backlight
comes up. The register data / version / feature / resets are validated.
Open: /sys/class/drm/card0 has no connector yet — rockchip_rgb_init isn't producing
one ("Cannot find any crtc"). Last mile of M4; needs a debug print in rgb_init + the
panel bus_format, and the pixels must be verified on the physical panel (can't be
checked over serial/ssh). Full recipe + next steps in display/README.md.
Also batch-2 config: GPIO_SYSFS, PWM_ROCKCHIP, crypto (aes/ccm/ctr/arc4), CFG80211,
DRM_ROCKCHIP/ROCKCHIP_VOP all =y; PSCI-style SMC removed via the psci-node deletion.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Move from the hand-built minimal DT to the vendor rv1106.dtsi (full SoC:
pinctrl, gpio×5, dmac, cru+grf_cru, all peripherals), with our lean board DTS
(rv1106-warden.dts) enabling only the wall-HMI's needs — no camera/ISP/CSI.
Two deltas made it boot on 6.18: overwrite boot-mode.h with the vendor's (extra
BOOT_* constants) and DELETE the psci node (no secure monitor → SMC fault →
"Attempted to kill the idle task"). Recipe in dts/README.md.
Verified on warden-c8a3 (uname 6.18.46, full WardenOS userspace): pinctrl,
gpio0-4, pl330 DMA, uart1/2/4 (ttyS1/2/4), i2c3, dw-wdt (watchdog0) all probe.
DRIVER-PARITY.md tracks the remaining ports (VOP display, AIC8800 wifi, rknpu,
usb2phy, saradc-compat, RGA) toward full parity with the 5.10 kernel.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Adding the eMMC dw_mmc node (mmc@ffa90000, clocks from cru + grf_cru) was all M3
needed. On warden-c8a3 the 6.18 kernel enumerates the eMMC at HS200
(mmcblk0 8GTF4R 7.28 GiB), mounts the ext4 rootfs, runs /sbin/init, and starts
every WardenOS daemon. Serial root login confirms:
Linux warden-c8a3 6.18.46 armv7l
ps: warden-flared warden-modbus warden-mikrotik warden-asic warden-ui warden-flight
Expected M4/M5 gaps are clean failures: the 5.10 aic8800 wifi/BT .ko won't load on
6.18 (vermagic), and no backlight/framebuffer yet (no VOP node). Next: M4 display,
M5 AIC8800 SDIO port, M6 the rest; plus a lean defconfig + Buildroot-on-6.18.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
The Linux 6.18.46 forward-port boots on the panel through our ported drivers,
verified on the serial console: earlycon, arch timer (BogoMIPS calibrated), our
clk-rv1106 CRU, pinctrl, and the mainline 8250 bound to uart2 clocked by our CRU
(ttyS2 16550A), then rootfs mount.
Two DT fixes got it past "Starting kernel":
- fdt placed high (load=0x08000000) so the bloated multi_v7 zImage (~20 MiB
decompressed) stops overrunning the DTB at 0xc00000 (was: r2=0, "invalid dtb").
- added the rockchip,rv1106-grf-cru node (grf-clock-controller child of grf) so
clk-rv1106's grf_ctx isn't NULL (was: panic in rockchip_clk_register_branches).
Console pinned to 115200 (readable on the CP2102 bench adapter; prod uses 1.5M).
The boot-image format and the A/B _b-slot safe-test method (which auto-reverted to
_a on every failed attempt) are in docs/m2-boot-on-c8a3.md. M3 next: lean defconfig
+ dw_mmc DT + our Buildroot userspace rebuilt on 6.18.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Investigated whether the RV1106 NPU (RKNPU) could do 3D rendering or other
graphical work as we port its driver to 6.18. Verdict: no. Read the vendored
rknpu driver directly — it executes a pre-compiled regcmd list from Rockchip's
closed RKNN compiler; no register ISA, no arbitrary-kernel submit path. Only the
vertex-transform stage (GEMM) maps at all, and rasterization/depth/texture/
shading/framebuffer have no mapping to a conv/pool op set — absent, not slow. For
every CNN-shaped graphical candidate the SoC already has a better fit (RGA 2D,
idle RKIVE classic-CV), and there's no camera. Recommend porting rknpu.ko only
for future non-visual inference, never for graphics.
Caveat flagged in the doc: the no-rasterizer claim is from the RKNN op taxonomy +
architecture, not register-level ground truth (TRM Part 2 is unpublished).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
M1 is complete (clk + pinctrl + mach compile clean); this reaches M2's build
milestone. multi_v7_defconfig + configs/m2-earlycon.fragment builds an 11.8 MB
zImage with clk-rv1106.o and pinctrl-rockchip.o (our rv1106 data) compiled into
the full tree — no rv1106 warnings. dts/rv1106-warden-m2.dts (CPU, GIC-400, arch
timer, 256 MiB RAM, GRF, the CRU, uart2 as snps,dw-apb-uart) compiles clean at
W=1 with earlycon=uart8250,mmio32,0xff4c0000. Reproducible via build-m2.sh.
Boot is the next step and is on-hardware/attended: package zImage + dtb, load on
a bench unit with a recovery net, watch for the earlycon "it's alive". PORT-VERIFY
before trusting a boot: DDR size/base, the CPU clock mux, console baud.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
The device counterpart to warden-modbus's master/scanner: request-frame in,
response-frame out, in host memory. CRC16 is byte-identical to the master
(poly 0xA001, low-first; known vector 01 03 00 00 00 01 -> 84 0A verified).
Implements the data plane — read/write holding & input registers, coils,
discrete inputs (FC 0x01-0x06, 0x0F, 0x10) + Report Slave ID (0x11) — with
exception replies (illegal function/address/value) and the two real-world
faults the master must survive: a device that silently ignores a request
(drop_next) and one that NAKs everything (force_exception). This is what the
modbus-master MC/DC harness drives against; MEI (0x2B/0x0E) is a follow-up.
11 tests, sim crate 25/25 green.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
The c8a3 brick was a memory-map fault no behavioural sim can catch: a
boot-loaded coprocessor firmware dropped at 0x40000, which is a reserved-memory
carve-out on Thunder-Boot boards but plain kernel RAM on ours. config-lint is
the static gate for it — parse the rkbin loader .ini for every LOADERn=Hpmcu
LOAD_ADDR, parse the target devicetree for reserved-memory ranges, fail if any
MCU load lands outside a reservation.
Tests encode the brick as a regression against the REAL Thunder-Boot .ini
(Hpmcu@0x40000): fails with no rtos@40000 node, passes once reserved; our
board's non-TB loader (no boot-loaded MCU) always passes. 6/6 green; CLI
verified against the on-disk rkbin .ini files.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Models the RV1106 reset ladder + boot-mode register on the MemBus seam, so
flared's devmem::hard_reset ladder and the boot-mode -> MaskRom recovery
maneuver are testable entirely on the host. Bakes in the two hardware facts
that cost real bench time as regression tests:
- the CRU global-reset register is 0xff3b0c08/0xfdb9; the magic at the wrong
offset 0xff3a0614 (from other Rockchip SoCs) is a SILENT NO-OP here;
- the boot-mode register 0xff020200 survives a warm reset (the mechanism that
makes "set MaskRom, then reset" drop the SoC into BootROM download), and a
power-on reset clears it.
6 tests (both rungs, pet, the wrong-offset no-op, MaskRom-survives-warm-reset,
POR-clears-request); the sim crate is 14/14 green.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
2-line DT-compat add to rockchip_board_dt_compat[] (rv1103 + rv1106), per the
breadth survey. Did NOT recreate the dropped CPU_RV1106 symbol (mainline IDs the
SoC purely via DT compat at runtime). clk + pinctrl + mach = the 3 core compile
components; DT + defconfig + full build remain for M2 (console boot).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
M1 pinctrl ported from vendor 5.10 (effort S, no API drift): enum, DRV/PULL/SMT
macros + 3 calc fns, case RV1106 in the 3 pull fns + RK3568 drive group, pin_banks
+ pin_ctrl, of_device_id (dropped CPU_RV1106 guard). pinctrl-rockchip.o 173KB, no
errors. iomux DRV/PULL/SMT offsets cross-validated against the upstream Simon Glass
v3 patch (match with the 0x10000 per-bank IOC base) -> the boot-critical iomux
PORT-VERIFY is retired via a 3rd independent source, no hardware. Upstream tracked
as a correctness oracle (doesn't apply to 6.18 cleanly; unmerged).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Per [maintainer]: forward-port the RV1106 SoC enablement from the vendor 5.10 tree to
6.18 LTS ourselves (no plan44), on our Buildroot. Verified mainline has ZERO
RV1106 support, so this is a whole-BSP port. docs/bringup.md = the console-first
milestone plan + method (sibling-delta from rv1126/rv1108, which exist in both
trees). M1 (clk driver) underway: gcc-8.3 builds 6.18; wired CLK_RV1106; ported
55 CRU macros + the panic_notifier header split + the armclk signature change
(flagged PORT-VERIFY for the CPU-mux, TRM-check needed). Captured in
rv1106-enablement/. Honest: first of ~120 files; multi-month effort.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
Grounded in a full survey of the flare-edge firmware: catalogs every hardware
seam (register/MemBus, resource-path env-override, RGA compile-time), the tiered
MC/DC target (our code real MC/DC via the uboot-ab pattern; blobs fault-injection),
the target-config-lint class that the sim CANNOT cover (the 0x40000 brick), and
the ordered plan. Notes the flared<-warden-sim Cargo dep needs a repo remote
([maintainer] go-ahead).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
New from-scratch SDK for WardenOS (RV1106). First substance: the hardware
simulator's core — a MemBus register/SRAM seam (one trait, real /dev/mem backend
on device + in-memory SimBus on host) and a faithful port of the HPMCU watchdog
firmware (hpmcu/watchdog/main.c) as HpmcuSim, with 8 tests validating boot-grace
fire, heartbeat-timeout, disarm stand-down, and the flared arm-within-grace safety
property (no boot-loop) — all off-device, in a virtual clock, in <1ms.
This closes the gap the Explore map flagged: flared's devmem.rs/hpmcu.rs are the
only register-touching modules with zero tests. README lays out the SDK vision
(modern kernel, tiered driver MC/DC, proper RGA/HPMCU/NPU simulator, own repo).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
