BFE Engineering
42fb386f60
Replace every em dash with real punctuation (rewrites, not hyphen swaps) in docs, code comments, scripts, configs, and the port records; convert en dashes, curly quotes, ellipsis glyphs, arrows, and section signs to ASCII; drop machine-writing tell phrases from living docs. ADR titles now use a colon. The M2 bring-up DTS model string carried an em dash into the patch series and its record echoes; fixed at both, and the full series re-verified to apply cleanly onto pristine 6.18.46. One comment in freshness.h deliberately names the em dash glyph the UI renders as the unknown mark; that is data, kept as prose naming it. Verified: cargo tests (sim, config-lint, rs485-bridge), shellcheck, both driver MC/DC harnesses, patches-apply.
105 lines
5.6 KiB
Markdown
105 lines
5.6 KiB
Markdown
# M2 boot bring-up on warden-c8a3 (live notes)
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Booting the self-built 6.18 kernel on real hardware (warden-c8a3), 2026-08-24.
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The build side (zImage + dtb) is in `../rv1106-enablement/`; this is the on-target
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half. **The safe-test framework and the boot-image format below are the reusable
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findings: they worked on the first hardware try.**
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## The safe test path (A/B slot _b, never touch _a)
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c8a3 is the desk-connected bench Warden: reachable over its USB-gadget ethernet
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(dev-build dropbear; address and bench credentials live in the private
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deployment notes: use `scp -O`, no sftp-server), plus the serial console at
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115200 and remotely switchable power. It runs an A/B
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firmware (boot_a=mmcblk0p5 / boot_b=mmcblk0p6, 32 MiB each; rootfs_a/_b; AvbABData
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in `misc` sector 4 / byte 2048).
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The test never risks the working system:
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1. Back up `boot_b` (`dd .../by-name/boot_b -> /userdata/boot_b.bak`).
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2. Write the test `boot.img` to **boot_b only**. `_a` (the shipped WardenOS) is
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untouched.
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3. Flip AvbABData to a **one-shot _b**: `craft_ab.py 14 0 1 15 1 0 1` -> A(prio14,
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tries0,ok1) B(prio15,tries1,ok0); write to `misc` sector 4. U-Boot's SPL then
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picks _b once, decrements tries->0, and boots it.
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4. If the test kernel fails/hangs, U-Boot auto-reverts to `_a` (SPL: "slot boot
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failed, resetting" -> next boot `A/B-slot: _a, successful: 1`). A hung kernel
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just needs a Zigbee power-cycle; `_a` boots WardenOS back. **Zero manual
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recovery needed: verified across three failed attempts.**
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`earlycon=uart8250,mmio32,0xff4c0000` is confirmed correct: it is in the live
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5.10 cmdline, and U-Boot's own DDR probe reports `Adding bank: 0x0 - 0x10000000`
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(256 MiB), so the M2 DT's memory node and earlycon are right.
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## The boot-image format (this was the whole fight)
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rockchip U-Boot (this build) needs a very specific `boot.img`, NOT a plain FIT:
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- **External-data FIT.** `mkimage -f its -E -p 0x800`. The FDT metadata stays tiny
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(totalsize ~ 1536 B, matching boot_a); the kernel/fdt/resource **data is
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appended** after it. A normal embedded-data FIT (totalsize = whole image) is
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rejected with `FIT: No fit blob` / `No FIT image`.
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- **A `resource` (multi) sub-image is mandatory.** rockchip reads the DTB via the
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`RESC:` path from a resource image containing `rk-kernel.dtb` (+ logos), built
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with `resource_tool --pack`. Without it: `Failed to load DTB, ret=-19`.
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- **Sysmem sentinel load addresses.** fdt `load=0xffffff00`, kernel
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`load=entry=0xffffff01`; U-Boot's sysmem places them (it chose kernel@0x8000,
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fdt@0xc00000). Real low addresses collided -> "No fit blob".
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- `CONFIG_FIT_SIGNATURE` is **off** in this U-Boot, so the image need not be
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signed. Template: `sdk/sysdrv/source/kernel/boot.its`; builder recipe:
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`sdk/project/scripts/mk-fitimage.sh` (`mkimage -E -p 0x800`).
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With the correct format, U-Boot loaded my kernel + my DTB and printed my DT model
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string (`Model: WardenOS 86-Panel (RV1106), M2 earlycon bring-up`), then
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`Starting kernel ...`.
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## Result: [x] M2 achieved, the 6.18 kernel boots on hardware
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Six attempts, each auto-recovering to `_a`, then a clean boot:
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```
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[0.000000] Linux version 6.18.46 ... #2 SMP
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[0.000000] CPU: ARMv7 Processor [410fc075]
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[0.000000] OF: fdt: Machine model: WardenOS 86-Panel (RV1106), M2 earlycon bring-up
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[0.000000] earlycon: uart8250 at MMIO32 0xff4c0000
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[0.000000] cma: Reserved 64 MiB at 0x0c000000
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[0.040693] Calibrating delay loop ... 48.00 BogoMIPS <- arch timer up
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[0.343810] pinctrl core: initialized pinctrl subsystem
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[1.968703] ff4c0000.serial: ttyS2 ... is a 16550A <- 8250 on our CRU clock
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```
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Two more bugs, found via the DEBUG_LL rebuild (`DEBUG_LL_UART_8250`, PHYS
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0xff4c0000, shift 2, 32-bit word + `earlyprintk`, the decompressor prints
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pre-MMU), then fixed:
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- **DTB overrun -> `r2=0` / `invalid dtb`.** The multi_v7 zImage decompresses to
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~20 MiB from 0x8000, overrunning the DTB at 0xc00000, so the decompressor handed
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the kernel a null DTB pointer. Fix: place the fdt high (`load=0x08000000`) in the
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FIT `.its` (see `boot5.its`). The real fix is a lean defconfig; multi_v7 is bloat.
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- **`grf_ctx` NULL deref in clk-rv1106.** `rockchip_clk_register_branches(grf_ctx,...)`
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crashed because the minimal DT had no `rockchip,rv1106-grf-cru` node to set
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`grf_ctx`. Fix: add the `grf-clock-controller` child to the grf syscon (now in
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`dts/rv1106-warden-m2.dts`).
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**Console baud gotcha:** `console=ttyS2,115200`. earlycon is readable at 115200
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(U-Boot leaves uart2 there), but the vendor's 1.5M console rate is garbage on the
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CP2102 bench adapter, so the M2 DT pins 115200 for readable bring-up; production
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overrides to 1.5M.
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## M3 (same session): [x] the full WardenOS runs on the 6.18 kernel
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Adding the eMMC `dw_mmc` node (`mmc@ffa90000`, clocks from cru + grf_cru) was the
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only change M3 needed: the mmc/ext4 drivers are already in-config. The kernel
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enumerated the eMMC at HS200, mounted the ext4 rootfs, ran `/sbin/init`, and
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started every WardenOS daemon. A serial root login confirms `uname -a` ->
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`Linux warden-c8a3 6.18.46 armv7l`, with `warden-flared/-modbus/-mikrotik/-asic/
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-ui/-flight` all running. Expected M4/M5 gaps show cleanly: the 5.10 aic8800 `.ko`
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won't load (vermagic -> M5), and there's no backlight/framebuffer yet (-> M4).
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**Console lesson applied:** with `console=ttyS2,115200` the whole boot is readable
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on the CP2102 (the 1.5M vendor rate is garbage on it). Serial login uses the same
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`c8a3_run.py` helper (dev-build bench credentials, see private deployment notes)
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as the 5.10 firmware: the userspace is unchanged.
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Next: M4 (VOP2 display + panel + touch), M5 (AIC8800 SDIO port + our 4 patches),
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M6 (RGA/watchdog/HPMCU/USB-OTG); plus a lean defconfig + Buildroot-on-6.18 cleanup.
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