BFE EngineeringandClaude Opus 4.8
869fcebe6f
Per [maintainer]: forward-port the RV1106 SoC enablement from the vendor 5.10 tree to 6.18 LTS ourselves (no plan44), on our Buildroot. Verified mainline has ZERO RV1106 support, so this is a whole-BSP port. docs/bringup.md = the console-first milestone plan + method (sibling-delta from rv1126/rv1108, which exist in both trees). M1 (clk driver) underway: gcc-8.3 builds 6.18; wired CLK_RV1106; ported 55 CRU macros + the panic_notifier header split + the armclk signature change (flagged PORT-VERIFY for the CPU-mux, TRM-check needed). Captured in rv1106-enablement/. Honest: first of ~120 files; multi-month effort. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
95 lines
4.9 KiB
Diff
95 lines
4.9 KiB
Diff
# WIP: RV1106 clock driver on Linux 6.18.46 (forward-ported from vendor 5.10). INCOMPLETE — compiles up to clk-rv1106.c:427.
|
|
--- a/drivers/clk/rockchip/Makefile 2026-08-23 06:27:10.000000000 -0600
|
|
+++ b/drivers/clk/rockchip/Makefile 2026-08-23 10:24:21.103809097 -0600
|
|
@@ -20,6 +20,7 @@
|
|
obj-$(CONFIG_CLK_PX30) += clk-px30.o
|
|
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
|
|
obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
|
|
+obj-$(CONFIG_CLK_RV1106) += clk-rv1106.o
|
|
obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
|
|
obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
|
|
obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
|
|
--- a/drivers/clk/rockchip/Kconfig 2026-08-23 06:27:10.000000000 -0600
|
|
+++ b/drivers/clk/rockchip/Kconfig 2026-08-23 10:24:43.911804398 -0600
|
|
@@ -30,6 +30,13 @@
|
|
help
|
|
Build the driver for RV1126 Clock Driver.
|
|
|
|
+config CLK_RV1106
|
|
+ bool "Rockchip RV1106 clock controller support"
|
|
+ depends on ARM || COMPILE_TEST
|
|
+ default y
|
|
+ help
|
|
+ Build the driver for RV1106 Clock Driver.
|
|
+
|
|
config CLK_RK3036
|
|
bool "Rockchip RK3036 clock controller support"
|
|
depends on ARM || COMPILE_TEST
|
|
--- a/drivers/clk/rockchip/clk.h 2026-08-23 06:27:10.000000000 -0600
|
|
+++ b/drivers/clk/rockchip/clk.h 2026-08-23 10:26:58.191806187 -0600
|
|
@@ -92,6 +92,64 @@
|
|
#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
|
|
#define RV1126_GLB_SRST_FST 0x408
|
|
#define RV1126_GLB_SRST_SND 0x40c
|
|
+
|
|
+/* RV1106 CRU register map — forward-ported from vendor 5.10 */
|
|
+#define RV1106_TOPCRU_BASE 0x10000
|
|
+#define RV1106_PERICRU_BASE 0x12000
|
|
+#define RV1106_VICRU_BASE 0x14000
|
|
+#define RV1106_NPUCRU_BASE 0x16000
|
|
+#define RV1106_CORECRU_BASE 0x18000
|
|
+#define RV1106_VEPUCRU_BASE 0x1A000
|
|
+#define RV1106_VOCRU_BASE 0x1C000
|
|
+#define RV1106_DDRCRU_BASE 0x1E000
|
|
+#define RV1106_SUBDDRCRU_BASE 0x1F000
|
|
+#define RV1106_VI_GRF_BASE 0x50000
|
|
+#define RV1106_VO_GRF_BASE 0x60000
|
|
+#define RV1106_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300)
|
|
+#define RV1106_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800)
|
|
+#define RV1106_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00)
|
|
+#define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE)
|
|
+#define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE)
|
|
+#define RV1106_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
|
|
+#define RV1106_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
|
|
+#define RV1106_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_TOPCRU_BASE)
|
|
+#define RV1106_GLB_SRST_FST (0xc08 + RV1106_TOPCRU_BASE)
|
|
+#define RV1106_GLB_SRST_SND (0xc0c + RV1106_TOPCRU_BASE)
|
|
+#define RV1106_SDIO_CON0 (0x1c + RV1106_VO_GRF_BASE)
|
|
+#define RV1106_SDIO_CON1 (0x20 + RV1106_VO_GRF_BASE)
|
|
+#define RV1106_SDMMC_CON0 (0x4 + RV1106_VI_GRF_BASE)
|
|
+#define RV1106_SDMMC_CON1 (0x8 + RV1106_VI_GRF_BASE)
|
|
+#define RV1106_EMMC_CON0 (0x20)
|
|
+#define RV1106_EMMC_CON1 (0x24)
|
|
+#define RV1106_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
|
|
+#define RV1106_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
|
|
+#define RV1106_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_PERICRU_BASE)
|
|
+#define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
|
|
+#define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
|
|
+#define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
|
|
+#define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
|
|
+#define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
|
|
+#define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
|
|
+#define RV1106_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
|
|
+#define RV1106_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
|
|
+#define RV1106_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_NPUCRU_BASE)
|
|
+#define RV1106_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
|
|
+#define RV1106_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
|
|
+#define RV1106_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_CORECRU_BASE)
|
|
+#define RV1106_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
|
|
+#define RV1106_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
|
|
+#define RV1106_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VEPUCRU_BASE)
|
|
+#define RV1106_VOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
|
|
+#define RV1106_VOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
|
|
+#define RV1106_VOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VOCRU_BASE)
|
|
+#define RV1106_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
|
|
+#define RV1106_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
|
|
+#define RV1106_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_DDRCRU_BASE)
|
|
+#define RV1106_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
|
|
+#define RV1106_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
|
|
+#define RV1106_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_SUBDDRCRU_BASE)
|
|
+#define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE)
|
|
+
|
|
#define RV1126_SDMMC_CON0 0x440
|
|
#define RV1126_SDMMC_CON1 0x444
|
|
#define RV1126_SDIO_CON0 0x448
|