BFE EngineeringandClaude Opus 4.8
4ee4dfcf88
First recursive code-review-harness pass over the authored SDK code (sim/,
config-lint, flowgen, drivers/{relays,freshness}, build/, ci.yml). Four parallel
dimension reviewers; all findings at every severity corrected per workspace rule.
Correctness / reliability:
- freshness.c min_budget_ms: use a `seen` flag, not `best==0`, as the empty
sentinel — a zero-tolerance (max_stale_ms==0) binding was silently widened to a
looser neighbour's budget. Regression test added; still 66/66 MC/DC.
- config-lint parse_reserved_ranges: match `reg` as a whole property token (ident
boundary before, `=` after) so `reg-names` / a `region-*` label no longer
mis-parses into a bogus reserved range.
- config-lint loader check: fail closed — flag any loader with a LOAD_ADDR that is
not a known-safe boot component, instead of only known MCU names, so a future
coprocessor ("Rtos"/"Bl32") can't slip past the 0x40000-brick gate.
- build-kernel.sh: sha256 verification is now mandatory (refuse to build if the pin
is missing) and the mktemp scratch tree is removed on exit (trap), while a
caller-provided WORK is left intact for CI artifact upload.
Test quality:
- freshness: added the age==max_stale boundary case and a clock-wraparound
(now < last_ok) fail-safe-to-UNKNOWN test.
- relays: unsetenv(WARDEN_GPIO_ROOT) at main() so the NULL-env arm is hermetic.
Security / CI:
- ci.yml: top-level `permissions: contents: read` (badges overrides to write);
pin taiki-e/install-action to commit SHA (v2.86.7).
Maintainability / docs:
- drivers/enforce-mcdc.sh: one shared, name-derived gate replaces the two
copy-pasted per-driver scripts; Makefiles call ../../enforce-mcdc.sh.
- docs/architecture.md: §3/§4/§6/§7 rewritten to match reality — NPU/RGA models,
config-lint, and the relays+freshness MC/DC harnesses are done; kernel §6 now
reflects the 5.10->6.18.46 forward-port (ADR-0001), not the superseded plan44/6.6.
- README: status blurb + layout table corrected (kernel/, .github/; stale ci/ and
patches/ descriptions fixed). hpmcu "8 tests" -> 7 in docs.
- freshness.{c,h}: ADR reference points at flare-edge ADR-0004 (warden-sdk's
ADR-0004 is the CI runner — number collision).
- normalize rustfmt drift across sim/ + config-lint.
All green: sim 37 tests, config-lint 8 tests, both drivers 100% MC/DC (relays
40/40, freshness 66/66), clippy clean under -D warnings, gitleaks clean.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
164 lines
11 KiB
Markdown
164 lines
11 KiB
Markdown
# warden-sdk architecture
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How the SDK makes WardenOS buildable, testable, and hardenable without a panel in
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the loop. Grounded in a full survey of the current flare-edge firmware (the seam
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inventory below is from that survey, not aspiration).
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## 1. The problem the seams solve
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The firmware touches RV1106 hardware through a *grab-bag* of mechanisms, each
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tested (or not) differently. Today:
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| Block | Where | Access | Test seam today | Fails on host by |
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|---|---|---|---|---|
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| Registers / SRAM (CRU reset, HPMCU mailbox) | `flared/src/devmem.rs`, `hpmcu.rs` | `/dev/mem` mmap `peek/poke32` | **none** — zero tests | (would fault; not exercised) |
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| HPMCU / RISC-V coproc | `flared/src/hpmcu.rs` | via devmem + firmware blob load | `WARDEN_HPMCU_FW` redirects the blob path only | env gate disables it |
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| NPU load | `ui-src/.../sysmon.c` | read `/proc/rknpu/load` | **none** — literal path | file absent → "NPU absent" |
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| RGA (2D blit) | `ui-src/.../warden_rga.c` | `librga improcess` + dma-heap ioctl | compile-time `#if WARDEN_USE_RGA` | `#if` off → LVGL software path |
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| RS485 daemon | `warden-modbus/modbus_engine.c` | `open("/dev/ttyS4")` | recompile `-DRS485_PORT=<pty>` | (recompiled for a pty) |
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| RS485 panel client | `ui-src/.../modbus.c` | `AF_UNIX` socket | `WARDEN_MODBUS_SOCK` env override | socket absent → "unavailable" |
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| Relays / GPIO | `ui-src/.../relays.c` | `/sys/class/gpio` sysfs | **none** — literal paths | path absent → "unavailable" |
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| Slot metadata | `flared/src/slotctl.rs` | `misc` partition + `/proc/cmdline` | `WARDEN_MISC_DEV`, `WARDEN_CMDLINE_FILE` env overrides | (redirected to scratch files) |
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Three patterns coexist: **compile-time `#if`** (RGA), **env-override** (modbus
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socket, misc dev, cmdline, hpmcu fw), and **fails-soft-because-the-path-is-absent**
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(NPU, relays, devmem-would-fault). The last is not a test seam — you cannot inject
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"relay 1 is ON" or "NPU at 80%", only "absent". The SDK's job is to turn all of
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these into **one deliberate seam per block** with a real backend and a sim backend.
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## 2. The seam taxonomy
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Two seam kinds cover everything above:
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- **Register/SRAM seam → a trait.** `MemBus` (`sim/src/membus.rs`): `peek32/poke32`
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at a physical address. Real backend = flared `devmem.rs` mmap; sim backend =
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`SimBus` (in-memory word map, `Clone` so two "cores" alias shared memory). The
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HPMCU watchdog and the CRU reset ladder both ride this. **Built.**
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- **Resource-path seam → env-override + injection.** For file/socket/sysfs paths
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(`/proc/rknpu/load`, `/sys/class/gpio/*`, `/dev/ttyS4`, `misc`), generalize the
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existing `WARDEN_MISC_DEV`/`WARDEN_MODBUS_SOCK` pattern into one rule: **every
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device/proc/sys path a driver opens is resolved through a single indirection
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(`warden_hw_path("npu.load")` in C, an env-overridable const in Rust)**, so a
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test points it at a fake file/fifo the sim writes. No LD_PRELOAD, no fake mounts.
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RGA stays compile-time — its `#if WARDEN_USE_RGA` already cleanly isolates the
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librga/dma-heap calls behind the always-compiled LVGL draw-unit glue; the sim
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backend is "a fake `improcess` that records the blits it was asked to do", swapped
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behind the same `#if`, so the offload *dispatch* logic gets tested even though the
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blit itself is modelled.
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## 3. The simulator (`sim/`)
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A host Rust library modelling the hardware the vendor SDK cannot, so driver and
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supervisor logic runs in CI with no panel.
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- **`membus` — register/SRAM bus.** Done. `MemBus` trait + `SimBus`.
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- **`hpmcu` — the RISC-V watchdog coprocessor.** Done. Faithful port of
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`hpmcu/watchdog/main.c`'s state machine (boot-grace, heartbeat-timeout, disarm,
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fire) against a `SimBus` mailbox, virtual clock, 7 tests including the
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arm-within-grace no-boot-loop safety property. This is the model that would have
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let the boot-loaded-watchdog logic be validated before the flash that bricked a
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bench unit (though the *layout* fault — a load address in unreserved kernel RAM —
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is a target-config check, §5, not a sim property).
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- **`cru` — reset ladder.** Done. `CruSim` on `MemBus` (so `flared::devmem::hard_reset`'s
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ladder is host-tested against the known glb_srst_fst / DW-watchdog registers), plus
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the boot-mode register's survives-warm-reset / cleared-by-POR behaviour (the MaskRom
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recovery maneuver). flared's `devmem` now has a matching `Bus` seam and unit tests
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that assert the shipped ladder pokes the confirmed offset, never the wrong-SoC one.
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- **`modbus` — RS-485 device end.** Done. `ModbusSlave`: a byte-in/byte-out RTU slave
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(CRC16 byte-identical to the master, FC 0x01–0x06/0x0F/0x10/0x11, exception replies,
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and fault injection — silent-drop and forced-NAK) so `warden-modbus`'s master can be
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hardened to MC/DC against realistic device behaviour with no serial hardware. MEI
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(0x2B/0x0E) identification is the documented follow-up.
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- **`npu` — NPU load model.** Done. `NpuSim` models `/proc/rknpu/load` (the exact
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"NPU load: N%" text the sysmon reads) behind the path seam, so the load-readout UI
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is host-testable. NPU *compute* is explicitly out of scope — no inference runs here.
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- **`rga` — 2D blitter offload.** Done. `RgaSim`, a recording `improcess` fake with a
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programmable `IM_STATUS`, so the RGA offload-dispatch and CPU-fallback logic is
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exercised behind the `#if WARDEN_USE_RGA` seam without librga; wired into the
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`rga_improcess` benchmark.
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- **Next:** MEI (0x2B/0x0E) Modbus identification; the Tier-2 driver *sources*
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(`modbus_engine.c`, `warden_rga.c`) migrate in with the flare-edge unification
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(ADR-0005) — their hardware ends are already modelled and tested above.
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Integration with flare-edge: flared implements `MemBus` for `/dev/mem` and gains
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`#[cfg(test)]` tests driving its real arm/beat logic against `HpmcuSim`. This needs
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warden-sdk reachable as a Cargo dependency in CI — i.e. a remote for this repo,
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which is a **[maintainer]-go-ahead item** (credential/remote creation). Until then the
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firmware-side seam and a local test double land in flare-edge, unified with `sim/`
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once the dependency exists. No duplication of *logic* — only the tiny trait.
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## 4. Driver hardening (the "port + harden to MC/DC" goal)
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"100% MC/DC on 100% of drivers" is infeasible literally: ~97% of driver LOC is
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vendor blobs (AIC8800 wifi = 88.5K lines). Tiered target:
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- **Tier 1 — our own hardware code → real MC/DC.** Method: the proven `tests/uboot-ab`
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pattern — extract the unit behind a small injectable seam, mock its world, build
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`-fcondition-coverage`, enforce with the shared `drivers/enforce-mcdc.sh` (gcc-14
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`gcov --conditions`) in the CI `mcdc` job. **Done here now:** `relays.c` (40/40
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conditions) and `freshness.c` (66/66), both at 100% MC/DC and CI-enforced. **Migrate
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in next:** the modbus master (`modbus_engine.c`) and the RGA wrapper's dispatch —
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their hardware ends are already modelled and tested in `sim/` (`modbus`, `rga`); the
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driver sources move in with the flare-edge unification (ADR-0005). The HPMCU
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supervisor and devmem reset ladder are covered Rust-side (`sim/hpmcu`, `sim/cru`).
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- **Tier 2 — near-mainline small drivers → branch coverage + fault injection.**
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- **Tier 3 — vendor blobs (AIC8800, MPP/ISP/RGA libs) → fault-injection hardening
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behind the seam,** not MC/DC. The AIC8800 SDIO-wedge Tier-1 fix + the designed
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reset-on-ETIMEDOUT recovery are this tier: test the *recovery* path against an
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injected wedge on the `MemBus`/SDIO seam, since the blob itself is untestable.
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Every seam gets a fault-injection mode (a wedged SDIO link, a stalled MCU
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heartbeat, an RGA timeout, a GPIO write EIO) so recovery code is tested against
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failure, not just the happy path.
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## 5. Target-config checks (a class the sim cannot cover)
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The brick was a *memory-map* fault: the boot-loaded MCU's load address (`0x40000`)
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is a reserved carve-out on Thunder-Boot boards but plain kernel RAM on ours. No
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behavioural sim catches that — it needs a **static check against the target DT**:
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"every address the MCU/coprocessor code loads to is inside a `reserved-memory`
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node." warden-sdk owns these config-lint checks (idblock loader `.ini` vs DT
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reservations, partition table vs image sizes, vermagic vs kernel) as CI gates, so a
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mistake is caught before a flash rather than on the bench.
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**Built:** `tools/config-lint` implements the first and most important of these —
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the MCU-load-vs-`reserved-memory` gate. It parses the rkbin loader `.ini` for
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every `LOADERn=Hpmcu` firmware and its `[LOADERn_PARAM] LOAD_ADDR`, parses the
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target devicetree (`.dts`, or `dtc -I dtb` output in CI) for `reserved-memory`
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ranges, and fails if any MCU load lands outside a reservation. Its test suite
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encodes the c8a3 brick itself: the real Thunder-Boot `.ini` (Hpmcu @ `0x40000`)
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fails against a DT with no `rtos@40000` node and passes once the reservation is
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added. **Next** target-config checks: partition-table-vs-image-size and
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vermagic-vs-kernel.
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## 6. Kernel forward-port (done — see ADR-0001)
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A self-built **Linux 6.18.46**, forward-ported directly from the vendor 5.10.160 tree
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onto our Buildroot LTS/uClibc base — **not** the plan44/OpenWrt 6.6 fork this section
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originally reached for. **ADR-0001 records why that was superseded:** plan44 drops
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Buildroot for OpenWrt/musl and ships no AIC8800 kmod, so it was a swap-out, not a
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forward-port. Mainline alone was not viable either (no DT/clk/display/RGA/NPU/
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flash-boot upstream for RV1106); the port reuses the already-in-mainline rv1126
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register data where it matches and carries our deltas as the reviewable `patches/`
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series. This is **done and hardware-verified on `warden-c8a3`** — clk, pinctrl, eMMC,
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GMAC, TRNG, OTP, SARADC/TSADC, RTC, USB host, PWM/backlight, VOP display, GT911 touch,
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AIC8800 wifi, RGA, I2S audio, HPMCU mailbox, the open NPU driver, and PVTM all boot.
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The dominant risk was the struct-ABI break (the VLAN saga), mitigated by shipping the
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kernel move as one matched boot+oem image, never a partial reflash.
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`build/build-kernel.sh` (the hermetic build) and the `patches-apply` CI gate keep the
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series honest against pristine 6.18.46; provenance is in `patches/README.md` and
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`kernel/rv1106-enablement/`.
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## 7. Order of work
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1. **Simulator core** — `membus`, `hpmcu`, the `cru` reset ladder, `modbus`, plus the
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`rga`/`npu` models. **Done.**
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2. **C-driver MC/DC harnesses** — `relays.c` and `freshness.c` at 100% MC/DC, CI-gated
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via the shared `drivers/enforce-mcdc.sh`. **Done** (the first C coverage gate).
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3. **flared devmem/hpmcu seam + tests** — firmware-side trait, unified with `sim/`
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once flare-edge consumes warden-sdk (a separate, [maintainer]-gated step). **Pending.**
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4. **Config-lint CI gates** (§5) — the brick-class of bug. **Done.**
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5. **Hermetic kernel build** (`build/build-kernel.sh` + the `patches-apply` gate). **Done.**
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6. **Kernel 5.10→6.18.46 forward-port** (§6, ADR-0001). **Done** (hardware-verified).
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