BFE EngineeringandClaude Opus 4.8
656b463039
Full clk port done: Kconfig/Makefile wired, 55 CRU macros, panic_notifier header split, armclk signature adaptation, CLK_FRAC_DIVIDER_NO_LIMIT->0. clk-rv1106.o (85KB) builds no-errors with gcc-8.3. Two PORT-VERIFY flags (CPU mux, UART frac baud) for TRM/hardware validation. First RV1106 driver ported vendor-5.10->6.18. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
53 lines
3.1 KiB
Markdown
53 lines
3.1 KiB
Markdown
# RV1106 → 6.18 forward-port — live status
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Target: **Linux 6.18.46** (vanilla, `flare-edge/research/linux-6.18.46/`), forward-ported
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from the **vendor 5.10.160** tree, no plan44 code, built with our
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`arm-rockchip830-...-gcc 8.3` (confirmed: **gcc 8.3 builds 6.18 fine**).
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## Confirmed feasibility facts
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- gcc 8.3 (our SDK toolchain) compiles the 6.18 kernel — no toolchain bump needed to start.
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- `multi_v7_defconfig` (ARM + rockchip) configures; `CLK_RV1106=y` wires in cleanly.
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- rv1106's siblings **rv1126/rv1108 exist in both trees**, so their 5.10→6.18 delta is a
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working template for the framework API changes.
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## M1 — clock driver (`clk-rv1106.c`, 1294 lines): ✅ COMPILES CLEAN on 6.18
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Build-fix loop against 6.18 — `clk-rv1106.o` (85732 bytes) builds with no errors.
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Fixed (captured in `clk/`):
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1. **Kconfig + Makefile hooks** — added `CONFIG_CLK_RV1106` (mirrors CLK_RV1126).
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2. **CRU register macros** — ported all 55 `RV1106_*` register-accessor `#define`s from the
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vendor `clk.h` into 6.18's `clk.h` (mainline has none).
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3. **Header split** — `panic_notifier_list` moved to `<linux/panic_notifier.h>` (kernel
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5.18); added the include.
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4. **`rockchip_clk_register_armclk` signature change** — 5.10 took
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`(num_parents, parent_clk, alt_parent_clk)`; 6.18 takes `(parent_names[], num_parents)`
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and drives the mux from `reg_data.mux_core_main/alt`. Adapted the call to the 6.18 form
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using a parent-names array (sibling-delta from rv1126). **⚠ PORT-VERIFY**: the mux input
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list `{ "gpll","cpll","apll" }` and the `mux_core_main/alt=2` mapping are a best-effort
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from the 5.10 intent (main=apll) — they set the **CPU clock source**, so they must be
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checked against the RV1106 `CORECLKSEL_CON` register map (TRM) and validated on hardware
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before trusting a boot. A wrong mux silently breaks boot.
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5. **`CLK_FRAC_DIVIDER_NO_LIMIT`** — Rockchip downstream-only frac-divider flag (6 uses on
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the UART frac clocks); mainline has no min/max opt-out, mapped to 0 (default limit).
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**⚠ PORT-VERIFY**: UART fractional baud accuracy.
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**Next:** the other core bring-up components (pinctrl, mach/timer, DT, defconfig) — being
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surveyed breadth-first in parallel to surface all their deltas before porting.
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## Honest scope
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This is the first driver of ~120 in the RV1106 BSP. The clk port alone is a multi-cycle
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effort of the four delta classes above; the whole bring-up (M1–M6 in `../docs/bringup.md`)
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is a multi-month kernel effort. Progress is real and the method is proven; correctness of
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boot-critical pieces (clock mux, PLL rates, DDR, pinctrl iomux) requires the TRM and
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on-hardware validation — which waits on c8a3's recovery and, ultimately, careful bring-up.
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## Layout
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```
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clk/
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clk-rv1106.c the ported driver (WIP, compiles to :427)
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rv1106-cru.h the clock-id dt-bindings header (staged)
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0001-rv1106-clk-framework-hooks.wip.patch Makefile/Kconfig/clk.h deltas vs vanilla 6.18
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```
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The full ported tree lives in `flare-edge/research/linux-6.18.46/` (scratch); this dir is
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the durable, reviewable capture, to become a proper patch series as milestones land.
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