BFE EngineeringandClaude Opus 4.8
6eed265f35
M1 pinctrl ported from vendor 5.10 (effort S, no API drift): enum, DRV/PULL/SMT macros + 3 calc fns, case RV1106 in the 3 pull fns + RK3568 drive group, pin_banks + pin_ctrl, of_device_id (dropped CPU_RV1106 guard). pinctrl-rockchip.o 173KB, no errors. iomux DRV/PULL/SMT offsets cross-validated against the upstream Simon Glass v3 patch (match with the 0x10000 per-bank IOC base) -> the boot-critical iomux PORT-VERIFY is retired via a 3rd independent source, no hardware. Upstream tracked as a correctness oracle (doesn't apply to 6.18 cleanly; unmerged). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
79 lines
5.0 KiB
Markdown
79 lines
5.0 KiB
Markdown
# RV1106 → 6.18 forward-port — live status
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Target: **Linux 6.18.46** (vanilla, `flare-edge/research/linux-6.18.46/`), forward-ported
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from the **vendor 5.10.160** tree, no plan44 code, built with our
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`arm-rockchip830-...-gcc 8.3` (confirmed: **gcc 8.3 builds 6.18 fine**).
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## Confirmed feasibility facts
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- gcc 8.3 (our SDK toolchain) compiles the 6.18 kernel — no toolchain bump needed to start.
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- `multi_v7_defconfig` (ARM + rockchip) configures; `CLK_RV1106=y` wires in cleanly.
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- rv1106's siblings **rv1126/rv1108 exist in both trees**, so their 5.10→6.18 delta is a
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working template for the framework API changes.
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## M1 — clock driver (`clk-rv1106.c`, 1294 lines): ✅ COMPILES CLEAN on 6.18
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Build-fix loop against 6.18 — `clk-rv1106.o` (85732 bytes) builds with no errors.
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Fixed (captured in `clk/`):
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1. **Kconfig + Makefile hooks** — added `CONFIG_CLK_RV1106` (mirrors CLK_RV1126).
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2. **CRU register macros** — ported all 55 `RV1106_*` register-accessor `#define`s from the
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vendor `clk.h` into 6.18's `clk.h` (mainline has none).
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3. **Header split** — `panic_notifier_list` moved to `<linux/panic_notifier.h>` (kernel
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5.18); added the include.
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4. **`rockchip_clk_register_armclk` signature change** — 5.10 took
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`(num_parents, parent_clk, alt_parent_clk)`; 6.18 takes `(parent_names[], num_parents)`
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and drives the mux from `reg_data.mux_core_main/alt`. Adapted the call to the 6.18 form
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using a parent-names array (sibling-delta from rv1126). **⚠ PORT-VERIFY**: the mux input
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list `{ "gpll","cpll","apll" }` and the `mux_core_main/alt=2` mapping are a best-effort
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from the 5.10 intent (main=apll) — they set the **CPU clock source**, so they must be
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checked against the RV1106 `CORECLKSEL_CON` register map (TRM) and validated on hardware
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before trusting a boot. A wrong mux silently breaks boot.
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5. **`CLK_FRAC_DIVIDER_NO_LIMIT`** — Rockchip downstream-only frac-divider flag (6 uses on
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the UART frac clocks); mainline has no min/max opt-out, mapped to 0 (default limit).
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**⚠ PORT-VERIFY**: UART fractional baud accuracy.
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## M1 — pinctrl (`pinctrl-rockchip.c/.h`): ✅ COMPILES CLEAN on 6.18
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`pinctrl-rockchip.o` (173688 bytes) builds no-errors. Transplanted from vendor 5.10 (effort S,
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zero API drift — the survey's assessment held): added `RV1106` to the type enum; a 159-line
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block of `RV1106_DRV/PULL/SMT_*` macros + 3 `rv1106_calc_*_reg_and_bit()` functions; `case
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RV1106:` in the 3 pull functions + the RK3568 drive-strength group; `rv1106_pin_banks[]` +
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`rv1106_pin_ctrl`; and the `rockchip,rv1106-pinctrl` of_device_id (dropping the vendor's
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`#ifdef CONFIG_CPU_RV1106` guard — mainline compiles all SoCs unconditionally). Captured as
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`pinctrl/0001-rv1106-pinctrl.patch`.
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- **PORT-VERIFY RESOLVED (iomux offsets):** the DRV/PULL/SMT per-bank offsets are confirmed by
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a THIRD independent source — the upstream Simon Glass v3 pinctrl patch. Its
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`rv1106_{drv,pull,smt}_offsets[]` match ours exactly once the 0x10000-strided per-bank IOC
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base is applied (e.g. vendor GPIO2 DRV `0x100C0` = `0x10000 + 0xc0`). Retires the "do not
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guess" iomux risk without hardware. (Note upstream uses per-bank IOC regmaps + low offsets;
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we use the vendor's full-offset form — same absolute register, both compile.)
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- **Still PORT-VERIFY:** GPIO4 bank pin-count (`pin_banks` says 24, DT `gpio-ranges` says 32) —
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carried from vendor unchanged; needs TRM/hardware.
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## M1 — mach + defconfig: NEXT
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Per the breadth survey's integration order: mach is a ~2-line DT-compat add to `rockchip.c`
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(do NOT recreate the dropped `CPU_RV1106` symbol); then the minimal M2 defconfig; then the DT
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(SoC nodes transplant + board-specific PORT-VERIFY: console UART, boot media, panel timings);
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then the first full kernel build toward an earlycon boot.
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## Upstream tracking (decision 2026-08-23)
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Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream
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RV1106 series (~35 patches, "New" state, does NOT apply cleanly to 6.18 — pinctrl v3 failed at
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`pinctrl-rockchip.c:3390`) is used as a **correctness oracle** for boot-critical PORT-VERIFY
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values (already retired the iomux offsets) and tracked for eventual convergence when it merges.
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## Honest scope
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This is the first driver of ~120 in the RV1106 BSP. The clk port alone is a multi-cycle
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effort of the four delta classes above; the whole bring-up (M1–M6 in `../docs/bringup.md`)
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is a multi-month kernel effort. Progress is real and the method is proven; correctness of
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boot-critical pieces (clock mux, PLL rates, DDR, pinctrl iomux) requires the TRM and
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on-hardware validation — which waits on c8a3's recovery and, ultimately, careful bring-up.
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## Layout
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```
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clk/
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clk-rv1106.c the ported driver (WIP, compiles to :427)
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rv1106-cru.h the clock-id dt-bindings header (staged)
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0001-rv1106-clk-framework-hooks.wip.patch Makefile/Kconfig/clk.h deltas vs vanilla 6.18
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```
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The full ported tree lives in `flare-edge/research/linux-6.18.46/` (scratch); this dir is
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the durable, reviewable capture, to become a proper patch series as milestones land.
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