BFE EngineeringandClaude Opus 4.8
c7ba8781a4
GMAC ✅ eth0 Link Up 100Mbps/Full on c8a3: ported rv1106_ops into mainline dwmac-rk.c (VOGRF RMII mode/speed + integrated FEPHY powerup via CON0; mainline set_speed/powerup split; bandgap trim omitted — analog opt the PHY runs without). &gmac enabled; uses the internal ethernet-phy@2. gmac/PORT-DONE.md. OTP ✅ now reads real data (px30_otp_read): 5211 02fe 084d 5231 ('MR1' chip id), no timeout. rng-otp/PORT-DONE.md updated. Batch A + GMAC complete — TRNG, OTP, GMAC all verified on hardware. DRIVER-PARITY updated. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
49 lines
2.1 KiB
Markdown
49 lines
2.1 KiB
Markdown
# TRNG + OTP port (batch A) — 6.18
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## TRNG (hardware RNG) — ✅ VERIFIED on warden-c8a3 (2026-08-25)
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rv1106's `rockchip,trngv1` is the same standalone TRNG_V1 IP as rk3588 (identical
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register map). Mainline `drivers/char/hw_random/rockchip-rng.c` already drives it.
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**Delta:** one OF-table entry reusing `rk3588_soc_data`:
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```c
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{ .compatible = "rockchip,rv1106-rng", .data = (void *)&rk3588_soc_data },
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```
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(The driver grabs clocks via `clk_bulk_get_all` and treats reset as optional, so
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rv1106's clock/reset names need no special handling.) Kconfig
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`HW_RANDOM_ROCKCHIP=y` (already set).
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**DT** (`rv1106-warden.dts`): override the dtsi `rng@ff448000` node —
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```dts
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&rng { compatible = "rockchip,rv1106-rng"; status = "okay"; };
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```
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**Evidence:** `/dev/hwrng` present, `rng_current = rockchip-rng`,
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`dd if=/dev/hwrng bs=16` → `c697 503d f9db 6b84 50e4 e1ee f232 b2ae` (real HW
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entropy, non-zero). Hardware entropy source for the panel's crypto/keys.
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## OTP / nvmem — ✅ VERIFIED on warden-c8a3 (2026-08-25)
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Reads real data: `dd .../rockchip-otp0/nvmem bs=1 count=16 | xxd` →
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`5211 02fe 084d 5231 0000 0000 3b15 0000` (contains "MR1" chip id) — no timeout.
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Mainline `drivers/nvmem/rockchip-otp.c` gains an `rv1106_data` + compatible.
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**Delta:**
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```c
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static const char * const rv1106_otp_clocks[] = {
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"usr", "sbpi", "apb", "phy", "arb", "pmc", /* matches DT clock-names */
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};
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static const struct rockchip_data rv1106_data = {
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.size = 0x80,
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.clks = rv1106_otp_clocks,
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.num_clks = ARRAY_SIZE(rv1106_otp_clocks),
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.reg_read = px30_otp_read, /* user-mode OTPC_USER interface */
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};
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/* OF: { "rockchip,rv1106-otp", &rv1106_data } */
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```
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Kconfig `NVMEM_ROCKCHIP_OTP=y`. **DT:** `&otp { status = "okay"; };` (the dtsi
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`otp@ff3d0000` node already carries compatible + the 6 clocks/resets).
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**First try** used `.reg_read = rk3588_otp_read` → `timeout during read setup`
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(rk3588 uses a different addressing path). Corrected to `px30_otp_read` — the
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mainline user-mode OTPC_USER read, the same sequence the vendor 5.10 driver used
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for rv1106 (its `rk3568_otp_read`). Confirmed: cell reads return real data.
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