BFE EngineeringandClaude Opus 4.8
869fcebe6f
Per [maintainer]: forward-port the RV1106 SoC enablement from the vendor 5.10 tree to 6.18 LTS ourselves (no plan44), on our Buildroot. Verified mainline has ZERO RV1106 support, so this is a whole-BSP port. docs/bringup.md = the console-first milestone plan + method (sibling-delta from rv1126/rv1108, which exist in both trees). M1 (clk driver) underway: gcc-8.3 builds 6.18; wired CLK_RV1106; ported 55 CRU macros + the panic_notifier header split + the armclk signature change (flagged PORT-VERIFY for the CPU-mux, TRM-check needed). Captured in rv1106-enablement/. Honest: first of ~120 files; multi-month effort. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
50 lines
2.9 KiB
Markdown
50 lines
2.9 KiB
Markdown
# RV1106 → 6.18 forward-port — live status
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Target: **Linux 6.18.46** (vanilla, `flare-edge/research/linux-6.18.46/`), forward-ported
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from the **vendor 5.10.160** tree, no plan44 code, built with our
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`arm-rockchip830-...-gcc 8.3` (confirmed: **gcc 8.3 builds 6.18 fine**).
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## Confirmed feasibility facts
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- gcc 8.3 (our SDK toolchain) compiles the 6.18 kernel — no toolchain bump needed to start.
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- `multi_v7_defconfig` (ARM + rockchip) configures; `CLK_RV1106=y` wires in cleanly.
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- rv1106's siblings **rv1126/rv1108 exist in both trees**, so their 5.10→6.18 delta is a
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working template for the framework API changes.
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## M1 — clock driver (`clk-rv1106.c`, 1284 lines): IN PROGRESS
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Build-fix loop against 6.18. Fixed so far (captured in `clk/`):
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1. **Kconfig + Makefile hooks** — added `CONFIG_CLK_RV1106` (mirrors CLK_RV1126).
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2. **CRU register macros** — ported all 55 `RV1106_*` register-accessor `#define`s from the
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vendor `clk.h` into 6.18's `clk.h` (mainline has none).
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3. **Header split** — `panic_notifier_list` moved to `<linux/panic_notifier.h>` (kernel
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5.18); added the include.
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4. **`rockchip_clk_register_armclk` signature change** — 5.10 took
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`(num_parents, parent_clk, alt_parent_clk)`; 6.18 takes `(parent_names[], num_parents)`
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and drives the mux from `reg_data.mux_core_main/alt`. Adapted the call to the 6.18 form
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using a parent-names array (sibling-delta from rv1126). **⚠ PORT-VERIFY**: the mux input
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list `{ "gpll","cpll","apll" }` and the `mux_core_main/alt=2` mapping are a best-effort
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from the 5.10 intent (main=apll) — they set the **CPU clock source**, so they must be
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checked against the RV1106 `CORECLKSEL_CON` register map (TRM) and validated on hardware
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before trusting a boot. A wrong mux silently breaks boot.
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**Next frontier:** `clk-rv1106.c:427` — `CLK_FRAC_DIVIDER_NO_LIMIT`, a Rockchip
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downstream-only fractional-divider flag absent from mainline 6.18; needs mapping to the
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mainline frac-divider behavior (likely define-as-0 if mainline defaults to no-limit, but
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verify the divider min/max semantics).
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## Honest scope
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This is the first driver of ~120 in the RV1106 BSP. The clk port alone is a multi-cycle
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effort of the four delta classes above; the whole bring-up (M1–M6 in `../docs/bringup.md`)
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is a multi-month kernel effort. Progress is real and the method is proven; correctness of
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boot-critical pieces (clock mux, PLL rates, DDR, pinctrl iomux) requires the TRM and
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on-hardware validation — which waits on c8a3's recovery and, ultimately, careful bring-up.
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## Layout
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```
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clk/
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clk-rv1106.c the ported driver (WIP, compiles to :427)
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rv1106-cru.h the clock-id dt-bindings header (staged)
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0001-rv1106-clk-framework-hooks.wip.patch Makefile/Kconfig/clk.h deltas vs vanilla 6.18
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```
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The full ported tree lives in `flare-edge/research/linux-6.18.46/` (scratch); this dir is
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the durable, reviewable capture, to become a proper patch series as milestones land.
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