BFE EngineeringandClaude Opus 4.8
880b043506
- tools/flowgen.py: generates docs/workflows/<name>.md — one outcome-first mermaid flowchart per workflow the SDK tests (hpmcu watchdog, modbus read, cru ladder, rga offload, relay drive, freshness contract), each stamped with its benchmark ns/op or 100% MC/DC result. Deterministic; reads the cargo-bench trend json. - drivers/README.md: honest Tier-1 (relays + freshness, 100% MC/DC here now) vs Tier-2 (modbus/rga — serious testing + fault-injection + benchmarks via sim models; driver sources migrate in with the flare-edge unification) per ADR-0002/0005. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
42 lines
2.5 KiB
Markdown
42 lines
2.5 KiB
Markdown
# drivers/ — our own hardened, hardware-facing drivers
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Per **ADR-0002** (tiered MC/DC) and **ADR-0005** (source-of-truth), our own
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hardware-facing code migrates here behind a HAL seam and is hardened. "100% MC/DC on
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100% of drivers" is infeasible (≈97% of kernel-driver LOC is vendor blobs — AIC8800
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alone is 88.5K lines); the realistic, honest target is tiered.
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## Tier 1 — real 100% MC/DC (here now, CI-enforced)
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Self-contained logic with a clean seam, measured to **100% MC/DC** (gcc-14
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`-fcondition-coverage`) by the CI `mcdc` job (`make -C drivers/*/test check`):
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| Driver | Seam | MC/DC |
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|---|---|---|
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| `relays/` | `relay_io` vtable (sysfs backend + in-memory fake) | 40/40 conditions, 100% |
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| `freshness/` | produce/render callbacks (the "no stale numbers" guard) | 66/66 conditions, 100% |
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**Adding a Tier-1 driver:** copy `<name>.{c,h}` here, put the hardware/OS calls behind
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a small injectable seam, then mirror `relays/test/` (a fake backend for the logic
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branches + a real backend over a scratch tree for the plumbing) and
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`enforce-mcdc.sh`. The CI job picks up any `drivers/*/test/Makefile` automatically.
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## Tier 2 — serious testing + fault-injection + benchmarks
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Drivers too large or too vendor/UI-coupled for literal MC/DC get fault-injection,
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branch coverage, and benchmarks against the simulator instead. Their **hardware side
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is already modelled and tested here** in `../sim/`:
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| Driver | Serious-testing status | SDK model |
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|---|---|---|
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| `modbus_engine.c` (RS485 master) | 11 pty scenarios + fault-injection + a compiled corpus walk (flare-edge `tools/modbus-sim/`, green) | `sim::modbus` RTU slave (11 tests, silent-drop/forced-NAK faults) + `modbus_read_holding` benchmark |
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| `warden_rga.c` (RGA offload) | offload-dispatch + CPU-fallback logic | `sim::rga` recording `improcess` fake (programmable IM_STATUS) + `rga_improcess` benchmark |
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| HPMCU supervisor (`hpmcu.rs`) | arm/beat/fire + boot-grace safety property | `sim::hpmcu` (8 tests) + `hpmcu_tick` benchmark |
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**Why the Tier-2 *source* isn't vendored here yet:** `modbus_engine.c` and
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`warden_rga.c` pull in shared UI headers (`platform.h`, `settings.h`, `lv_*`) and
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librga. Copying those in would duplicate exactly the shared surface the
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**flare-edge↔warden-sdk unification** (ADR-0003/0005, a separate [maintainer]-gated step) is
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meant to resolve cleanly. So the Tier-2 *models* (the hardware ends) live here now;
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the Tier-2 *driver sources* migrate in with the unification, at which point their
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existing flare-edge harnesses point at this repo.
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