BFE EngineeringandClaude Opus 4.8
d50934d048
M1 is complete (clk + pinctrl + mach compile clean); this reaches M2's build milestone. multi_v7_defconfig + configs/m2-earlycon.fragment builds an 11.8 MB zImage with clk-rv1106.o and pinctrl-rockchip.o (our rv1106 data) compiled into the full tree — no rv1106 warnings. dts/rv1106-warden-m2.dts (CPU, GIC-400, arch timer, 256 MiB RAM, GRF, the CRU, uart2 as snps,dw-apb-uart) compiles clean at W=1 with earlycon=uart8250,mmio32,0xff4c0000. Reproducible via build-m2.sh. Boot is the next step and is on-hardware/attended: package zImage + dtb, load on a bench unit with a recovery net, watch for the earlycon "it's alive". PORT-VERIFY before trusting a boot: DDR size/base, the CPU clock mux, console baud. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
106 lines
6.6 KiB
Markdown
106 lines
6.6 KiB
Markdown
# RV1106 → 6.18 forward-port — live status
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Target: **Linux 6.18.46** (vanilla, `flare-edge/research/linux-6.18.46/`), forward-ported
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from the **vendor 5.10.160** tree, no plan44 code, built with our
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`arm-rockchip830-...-gcc 8.3` (confirmed: **gcc 8.3 builds 6.18 fine**).
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## Confirmed feasibility facts
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- gcc 8.3 (our SDK toolchain) compiles the 6.18 kernel — no toolchain bump needed to start.
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- `multi_v7_defconfig` (ARM + rockchip) configures; `CLK_RV1106=y` wires in cleanly.
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- rv1106's siblings **rv1126/rv1108 exist in both trees**, so their 5.10→6.18 delta is a
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working template for the framework API changes.
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## M1 — clock driver (`clk-rv1106.c`, 1294 lines): ✅ COMPILES CLEAN on 6.18
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Build-fix loop against 6.18 — `clk-rv1106.o` (85732 bytes) builds with no errors.
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Fixed (captured in `clk/`):
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1. **Kconfig + Makefile hooks** — added `CONFIG_CLK_RV1106` (mirrors CLK_RV1126).
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2. **CRU register macros** — ported all 55 `RV1106_*` register-accessor `#define`s from the
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vendor `clk.h` into 6.18's `clk.h` (mainline has none).
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3. **Header split** — `panic_notifier_list` moved to `<linux/panic_notifier.h>` (kernel
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5.18); added the include.
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4. **`rockchip_clk_register_armclk` signature change** — 5.10 took
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`(num_parents, parent_clk, alt_parent_clk)`; 6.18 takes `(parent_names[], num_parents)`
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and drives the mux from `reg_data.mux_core_main/alt`. Adapted the call to the 6.18 form
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using a parent-names array (sibling-delta from rv1126). **⚠ PORT-VERIFY**: the mux input
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list `{ "gpll","cpll","apll" }` and the `mux_core_main/alt=2` mapping are a best-effort
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from the 5.10 intent (main=apll) — they set the **CPU clock source**, so they must be
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checked against the RV1106 `CORECLKSEL_CON` register map (TRM) and validated on hardware
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before trusting a boot. A wrong mux silently breaks boot.
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5. **`CLK_FRAC_DIVIDER_NO_LIMIT`** — Rockchip downstream-only frac-divider flag (6 uses on
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the UART frac clocks); mainline has no min/max opt-out, mapped to 0 (default limit).
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**⚠ PORT-VERIFY**: UART fractional baud accuracy.
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## M1 — pinctrl (`pinctrl-rockchip.c/.h`): ✅ COMPILES CLEAN on 6.18
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`pinctrl-rockchip.o` (173688 bytes) builds no-errors. Transplanted from vendor 5.10 (effort S,
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zero API drift — the survey's assessment held): added `RV1106` to the type enum; a 159-line
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block of `RV1106_DRV/PULL/SMT_*` macros + 3 `rv1106_calc_*_reg_and_bit()` functions; `case
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RV1106:` in the 3 pull functions + the RK3568 drive-strength group; `rv1106_pin_banks[]` +
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`rv1106_pin_ctrl`; and the `rockchip,rv1106-pinctrl` of_device_id (dropping the vendor's
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`#ifdef CONFIG_CPU_RV1106` guard — mainline compiles all SoCs unconditionally). Captured as
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`pinctrl/0001-rv1106-pinctrl.patch`.
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- **PORT-VERIFY RESOLVED (iomux offsets):** the DRV/PULL/SMT per-bank offsets are confirmed by
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a THIRD independent source — the upstream Simon Glass v3 pinctrl patch. Its
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`rv1106_{drv,pull,smt}_offsets[]` match ours exactly once the 0x10000-strided per-bank IOC
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base is applied (e.g. vendor GPIO2 DRV `0x100C0` = `0x10000 + 0xc0`). Retires the "do not
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guess" iomux risk without hardware. (Note upstream uses per-bank IOC regmaps + low offsets;
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we use the vendor's full-offset form — same absolute register, both compile.)
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- **Still PORT-VERIFY:** GPIO4 bank pin-count (`pin_banks` says 24, DT `gpio-ranges` says 32) —
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carried from vendor unchanged; needs TRM/hardware.
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## M1 — mach: ✅ DONE
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`mach-rockchip` RV1106/RV1103 SoC recognition added as a DT-compat entry (no
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`CPU_RV1106` symbol recreated). Captured as `mach/0001-rv1106-soc-recognition.patch`.
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**M1 is complete: clk + pinctrl + mach all compile clean on 6.18.**
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## M2 — earlycon build: ✅ DONE (boot pending hardware)
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The first full kernel build with our SoC drivers, 2026-08-24:
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- **`multi_v7_defconfig` + `configs/m2-earlycon.fragment` builds an 11.8 MB zImage**
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with `clk-rv1106.o` (85732 B) and `pinctrl-rockchip.o` (173688 B, our rv1106 data)
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compiled *into the full tree* — no rv1106 warnings/errors. Reproducible via
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`build-m2.sh`.
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- **`dts/rv1106-warden-m2.dts` → `rv1106-warden-m2.dtb` compiles clean** (W=1, no dtc
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warnings). A deliberately minimal DT — CPU (cortex-a7), GIC-400, arch timer, 256 MiB
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RAM, GRF, the CRU (our clk-rv1106), and uart2 (`snps,dw-apb-uart`, the console) —
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with `earlycon=uart8250,mmio32,0xff4c0000` so the first print reuses the loader's
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divisor before any clock/pinctrl probe.
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**Still PORT-VERIFY before a boot is trusted:** memory size/base (256 MiB @ 0x0 assumed
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— the loader usually patches this); the CPU clock mux in clk-rv1106 (§M1 item 4); the
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console baud (1.5M assumed). A wrong DDR/clock value silently hangs before or just after
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earlycon.
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## M2 — boot: NEXT (on hardware)
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Package `zImage` + `rv1106-warden-m2.dtb` into a boot image and load on a bench unit
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(c8a3 / w7159, both with a proven recovery net), watching the debug UART — or the
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coprocessor USB console (R5) — for the earlycon "it's alive". A hang is expected to be
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one of the PORT-VERIFY values above; iterate with recovery ready. This is an attended
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step (brick-adjacent), not an unattended one.
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Then M3: `dw_mmc` DT + rootfs on our Buildroot userspace.
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## Upstream tracking (decision 2026-08-23)
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Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream
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RV1106 series (~35 patches, "New" state, does NOT apply cleanly to 6.18 — pinctrl v3 failed at
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`pinctrl-rockchip.c:3390`) is used as a **correctness oracle** for boot-critical PORT-VERIFY
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values (already retired the iomux offsets) and tracked for eventual convergence when it merges.
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## Honest scope
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This is the first driver of ~120 in the RV1106 BSP. The clk port alone is a multi-cycle
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effort of the four delta classes above; the whole bring-up (M1–M6 in `../docs/bringup.md`)
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is a multi-month kernel effort. Progress is real and the method is proven; correctness of
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boot-critical pieces (clock mux, PLL rates, DDR, pinctrl iomux) requires the TRM and
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on-hardware validation — which waits on c8a3's recovery and, ultimately, careful bring-up.
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## Layout
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```
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clk/ clk-rv1106.c + rv1106-cru.h + framework-hooks patch (M1)
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pinctrl/ 0001-rv1106-pinctrl.patch (M1)
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mach/ 0001-rv1106-soc-recognition.patch (M1)
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dts/ rv1106-warden-m2.dts minimal earlycon board DT (M2)
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configs/ m2-earlycon.fragment defconfig delta over multi_v7 (M2)
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build-m2.sh reproducible M2 build (zImage + dtb)
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```
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The full ported tree lives in `flare-edge/research/linux-6.18.46/` (scratch); this dir is
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the durable, reviewable capture, to become a proper patch series as milestones land.
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