BFE EngineeringandClaude Fable 5
16368bb871
Decision/directive lines keep their dates and content, drop the name; hands-on confirmations become "confirmed by hand at the panel"; a dangling CLAUDE.md reference becomes "repo policy". Upstream vendor author attributions in the GPL kernel sources (MODULE_AUTHOR, copyright headers, LKML citations) are third-party legal attributions and stay. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_018HUayid7W5w7jBdb9Rrj1K
72 lines
4.0 KiB
Markdown
72 lines
4.0 KiB
Markdown
# RV1106 → Linux 6.18 forward-port (self-built, from vendor 5.10)
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**Decision (2026-08-23):** forward-port the RV1106 SoC enablement from the
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Rockchip **vendor 5.10** tree straight to **Linux 6.18 LTS**, ourselves, using **no
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plan44 code**, built on **our Buildroot 2025.02 LTS + uClibc**. We own the tree.
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## The reality this rests on (verified, not assumed)
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Vanilla mainline (6.6.93 and 6.18) has **zero** RV1106 support — no devicetree, no
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clock driver, no pinctrl data, not one `rv1106` reference in `arch/arm` or
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`drivers/`. So "the newest kernel" is a generic ARM kernel that cannot boot this
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SoC. What we forward-port is the **entire RV1106 BSP**: ~120 files in the vendor
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5.10 tree touch `rv1106` (DT, clk, pinctrl, mach/PM, VOP display, mmc, and the
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out-of-tree AIC8800/RGA/MPP). This is a large, multi-milestone kernel effort;
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it is delivered incrementally, console-first.
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## Method (how each piece is ported)
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- **Framework drivers → sibling-delta.** clk and pinctrl are driven by the shared
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rockchip framework (`drivers/clk/rockchip/clk.c`, `pinctrl-rockchip.c`). RV1106's
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siblings **rv1126 and rv1108 exist in BOTH vendor-5.10 and mainline-6.18**, so
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their 5.10→6.18 delta is the exact recipe for how the framework API changed —
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we apply that recipe to rv1106's data (`clk-rv1106.c` = 1284 lines;
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`rv1106-cru.h` clock IDs; the rv1106 pinctrl table). This turns "adapt to APIs
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we have to guess" into "copy a diff a sibling already proves."
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- **SoC-unique code → forward-port + build-fix-build.** `mach-rockchip`
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(machine, `rockchip_hptimer`, `rv1106_pm`/`rv1106_sleep.S`), the CRU/GRF glue,
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and the board DT have no sibling; port directly and iterate on the 6.18 build.
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- **Mainline-present drivers → just wire DT + clocks.** 8250-dw UART, dw_mmc
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(SDIO/eMMC), dw-apb i2c, rockchip gpio/pinctrl core, pwm, dw-wdt watchdog are all
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in mainline 6.18 — we do **not** port them, we supply the DT nodes + clock/reset
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phandles and let the mainline drivers bind.
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- **Out-of-tree drivers → port the driver.** AIC8800 wifi (plan44 has none; ours),
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RGA/MPP kernel bits (assess vs need — the 86-Panel has no camera), carrying our
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Tier-1 SDIO-wakeup fix forward.
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- **Our 4 kernel patches** (panel-mcu-reset/logo, watchdog-enable, usb-otg
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dual-role, recovery-splash) → re-apply against 6.18 (line offsets + some DT
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bindings changed).
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## Bring-up milestones (console-first order)
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- **M0 — buildable base.** 6.18.46 tree + our Buildroot/uClibc toolchain builds a
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generic ARM kernel; a `rv1106_defconfig` forward-ported from vendor 5.10.
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- **M1 — SoC compiles.** `mach-rockchip` RV1106 select + `clk-rv1106` +
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rv1106 pinctrl data + `rv1106-cru.h` compile clean against 6.18 (no boot yet).
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- **M2 — earlycon boot.** DT (`rv1106.dtsi` core) + clk + pinctrl + 8250-dw →
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kernel prints to the RV1106 UART. The first "it's alive."
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- **M3 — rootfs boot.** dw_mmc + DT → eMMC/SD rootfs, userspace up on our Buildroot.
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- **M4 — display.** VOP2 + the RGB666 720×720 panel + GT911 touch + PWM backlight →
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the LVGL UI renders.
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- **M5 — wifi + our patches.** AIC8800 SDIO driver ported (+ Tier-1 fix); the 4
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custom kernel patches re-applied.
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- **M6 — the rest.** RGA (UI accel), watchdog, HPMCU coprocessor, USB-OTG dual role.
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## Regression (so a 6.18 port doesn't reintroduce the struct-ABI bug class)
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The warden-sdk simulator + MC/DC harness are how we hold the line: `HpmcuSim` and
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the register/`MemBus` seam test the supervisor/reset logic off the ported kernel;
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the `relays-mcdc` pattern extends to each ported driver we own; and a
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**config-lint CI gate** (the class that bricked c8a3 — a load address in unreserved
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kernel RAM) checks the DT reservations against the drivers on every build.
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## Layout (this repo)
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```
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kernel/
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rv1106-enablement/ the ported RV1106 BSP as it lands (patches/files on 6.18)
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docs/bringup.md this plan
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```
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The 6.18.46 source + the vendor 5.10 tree stay in `flare-edge/research/` and
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`flare-edge/.../sdk/` respectively (references, not committed here).
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