NoahandClaude Opus 5
f6add60a9c
Issue #160: the USB ethernet link on the OTG port stops passing traffic and the host controller is later declared dead ("xHCI host not responding to stop endpoint command", "HC died"). Root cause. The phy's OTG state machine and charger detection only make sense while the port is a peripheral. This board has no ID source, so in host role their inputs are meaningless: rockchip_usb2phy_otg_sm_work() reaches OTG_STATE_B_IDLE with vbus asserted, schedules rockchip_chg_detect_work(), and a DCP verdict calls rockchip_usb2phy_power_off(). That suspends the phy and drops the 480M clkout the controller's core runs on, while a device is enumerated and working. The controller then stops clocking with its register block still readable, so it reports itself healthy: USBCMD keeps RS set, USBSTS reads 0, PORTSC still shows CCS and PED. Only MFINDEX gives it away by no longer advancing. Nothing completes from that point, and the first transmit afterwards times out. The recovery path cannot help either, because xhci_halt() needs the core clock to update USBSTS.HCH, so it times out and xhci_reset() returns early without ever writing USBCMD.HCRST. dwc3 already calls phy_set_mode() on every role change, but this driver implemented no .set_mode, so the phy never learned the role. Implement it, track the role per port, and return early from both work functions in host role. The check is inside the functions because both have direct callers besides the scheduled work. This keeps dr_mode "otg" and runtime role switching. Setting dr_mode to "host" also avoids the fault, by skipping the same state machine, but compiles out the gadget needed for flashing, recovery and pairing. Measured on warden-c8a3, per arm, transmit packets and xhci interrupts delivered after the stated idle: idle 0 s +9, +10, +9 packets +170, +176, +188 interrupts idle 120 s +0, +0, +0 packets +0, +0, +0 interrupts Also drops 28-dwc3-otg-no-live-reinit.patch. It guarded dwc3_otg_host_init() against re-entry on a live controller, but that path never executes here: GSTS reads OTG IP clear and instrumentation logged no entries on either the hardware irq or the guard site. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MVGTC78dgCGfRANNKjoPea
95 lines
2.8 KiB
Diff
95 lines
2.8 KiB
Diff
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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@@ -203,6 +203,7 @@
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* @event_nb: hold event notification callback.
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* @state: define OTG enumeration states before device reset.
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* @mode: the dr_mode of the controller.
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+ * @host_mode: the port is currently acting as a USB host.
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*/
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struct rockchip_usb2phy_port {
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struct phy *phy;
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@@ -222,6 +223,7 @@
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struct notifier_block event_nb;
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enum usb_otg_state state;
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enum usb_dr_mode mode;
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+ bool host_mode;
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};
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/**
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@@ -649,11 +651,52 @@
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return 0;
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}
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+/*
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+ * The OTG port's state machines only make sense while the port is a
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+ * peripheral. In host role their inputs are meaningless on a board with no
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+ * ID source: charger detection drives the analog front end of a port that is
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+ * already enumerating a device, and its DCP verdict ends in
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+ * rockchip_usb2phy_power_off(), which suspends the phy and drops the 480M
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+ * clkout that the host controller's core runs on. The controller then stops
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+ * clocking with its registers still readable, so it reports itself healthy
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+ * while no transfer ever completes.
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+ *
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+ * dwc3 already calls phy_set_mode() on every role change, but this driver
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+ * implemented no .set_mode, so the phy never learned the role. Track it and
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+ * keep both state machines out of host role.
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+ */
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+static int rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode,
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+ int submode)
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+{
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+ struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
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+
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+ if (rport->port_id != USB2PHY_PORT_OTG)
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+ return 0;
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+
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+ switch (mode) {
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+ case PHY_MODE_USB_HOST:
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+ if (!rport->host_mode) {
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+ rport->host_mode = true;
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+ cancel_delayed_work_sync(&rport->otg_sm_work);
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+ cancel_delayed_work_sync(&rport->chg_work);
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+ }
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+ break;
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+ case PHY_MODE_USB_DEVICE:
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+ rport->host_mode = false;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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static const struct phy_ops rockchip_usb2phy_ops = {
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.init = rockchip_usb2phy_init,
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.exit = rockchip_usb2phy_exit,
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.power_on = rockchip_usb2phy_power_on,
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.power_off = rockchip_usb2phy_power_off,
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+ .set_mode = rockchip_usb2phy_set_mode,
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.owner = THIS_MODULE,
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};
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@@ -667,6 +710,10 @@
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unsigned long delay;
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bool vbus_attach, sch_work, notify_charger;
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+ /* In host role this machine can only get the answer wrong. */
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+ if (rport->host_mode)
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+ return;
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+
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vbus_attach = property_enabled(rphy->grf,
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&rport->port_cfg->utmi_bvalid);
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@@ -825,6 +872,10 @@
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bool is_dcd, tmout, vout, vbus_attach;
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unsigned long delay;
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+ /* Never probe the front end of a port that is hosting a device. */
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+ if (rport->host_mode)
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+ return;
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+
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vbus_attach = property_enabled(rphy->grf, &rport->port_cfg->utmi_bvalid);
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dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
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