blueflare/bfe-core1106-sdk
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

kernel: M3 DONE — full WardenOS boots on the self-built 6.18 kernel

Browse Source 
Adding the eMMC dw_mmc node (mmc@ffa90000, clocks from cru + grf_cru) was all M3
needed. On warden-c8a3 the 6.18 kernel enumerates the eMMC at HS200
(mmcblk0 8GTF4R 7.28 GiB), mounts the ext4 rootfs, runs /sbin/init, and starts
every WardenOS daemon. Serial root login confirms:

  Linux warden-c8a3 6.18.46 armv7l
  ps: warden-flared warden-modbus warden-mikrotik warden-asic warden-ui warden-flight

Expected M4/M5 gaps are clean failures: the 5.10 aic8800 wifi/BT .ko won't load on
6.18 (vermagic), and no backlight/framebuffer yet (no VOP node). Next: M4 display,
M5 AIC8800 SDIO port, M6 the rest; plus a lean defconfig + Buildroot-on-6.18.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
This commit is contained in:
BFE Engineering
2026-08-24 20:40:53 -06:00
co-authored by Claude Opus 4.8
parent f3087399f2
commit b5a448fa84
3 changed files with 66 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
kernel/rv1106-enablement/dts/rv1106-warden-m2.dts
+22 -3
View File
@@ -39,9 +39,8 @@
stdout-path = "serial2:115200n8";
/*
* earlycon with no baud = reuse the divisor the bootloader left in
* uart2, so the first prints work regardless of our clock tree. The ttyS console is
* pinned to 115200 to stay readable on the CP2102 bench adapter;
* production WardenOS uses 1.5M.
* uart2, so the first prints work regardless of our clock tree. The
* ttyS console rate (1.5M) is PORT-VERIFY against the board.
*/
bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyS2,115200n8 earlyprintk rootwait";
};
@@ -123,4 +122,24 @@
clock-names = "baudclk", "apb_pclk";
status = "okay";
};
/* M3: the eMMC (dw_mmc). Lets the kernel enumerate mmcblk0 and mount an
* ext4 rootfs. ciu-drive/ciu-sample clocks come from grf_cru, so the
* grf-clock-controller node above is a hard dependency. */
emmc: mmc@ffa90000 {
compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0xffa90000 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>,
<&grf_cru SCLK_EMMC_DRV>, <&grf_cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
rockchip,use-v2-tuning;
bus-width = <8>;
non-removable;
cap-mmc-highspeed;
mmc-hs200-1_8v;
status = "okay";
};
};