kernel: M3 DONE — full WardenOS boots on the self-built 6.18 kernel
Adding the eMMC dw_mmc node (mmc@ffa90000, clocks from cru + grf_cru) was all M3 needed. On warden-c8a3 the 6.18 kernel enumerates the eMMC at HS200 (mmcblk0 8GTF4R 7.28 GiB), mounts the ext4 rootfs, runs /sbin/init, and starts every WardenOS daemon. Serial root login confirms: Linux warden-c8a3 6.18.46 armv7l ps: warden-flared warden-modbus warden-mikrotik warden-asic warden-ui warden-flight Expected M4/M5 gaps are clean failures: the 5.10 aic8800 wifi/BT .ko won't load on 6.18 (vermagic), and no backlight/framebuffer yet (no VOP node). Next: M4 display, M5 AIC8800 SDIO port, M6 the rest; plus a lean defconfig + Buildroot-on-6.18. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
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co-authored by
Claude Opus 4.8
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f3087399f2
commit
b5a448fa84
@@ -84,8 +84,19 @@ pre-MMU), then fixed:
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CP2102 bench adapter — so the M2 DT pins 115200 for readable bring-up; production
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CP2102 bench adapter — so the M2 DT pins 115200 for readable bring-up; production
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overrides to 1.5M.
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overrides to 1.5M.
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## Next (M3)
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## M3 (same session): ✅ the full WardenOS runs on the 6.18 kernel
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The kernel mounts the 5.10 rootfs_b but the userspace/modules are 5.10 (vermagic
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Adding the eMMC `dw_mmc` node (`mmc@ffa90000`, clocks from cru + grf_cru) was the
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mismatch). M3: lean RV1106 defconfig, `dw_mmc`/`sdhci` DT (eMMC already probes —
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only change M3 needed — the mmc/ext4 drivers are already in-config. The kernel
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`MMC0: HS200`), and our Buildroot userspace rebuilt on 6.18.
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enumerated the eMMC at HS200, mounted the ext4 rootfs, ran `/sbin/init`, and
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started every WardenOS daemon. A serial root login confirms `uname -a` →
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`Linux warden-c8a3 6.18.46 armv7l`, with `warden-flared/-modbus/-mikrotik/-asic/
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-ui/-flight` all running. Expected M4/M5 gaps show cleanly: the 5.10 aic8800 `.ko`
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won't load (vermagic → M5), and there's no backlight/framebuffer yet (→ M4).
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**Console lesson applied:** with `console=ttyS2,115200` the whole boot is readable
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on the CP2102 (the 1.5M vendor rate is garbage on it). Serial login uses the same
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`c8a3_run.py` [bench-creds] helper as the 5.10 firmware — the userspace is unchanged.
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Next: M4 (VOP2 display + panel + touch), M5 (AIC8800 SDIO port + our 4 patches),
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M6 (RGA/watchdog/HPMCU/USB-OTG); plus a lean defconfig + Buildroot-on-6.18 cleanup.
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@@ -95,11 +95,35 @@ Three bring-up bugs were found and fixed on hardware, all captured in the DT:
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comes up far enough to clock the UART and the arch timer on hardware. A wrong CPU
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comes up far enough to clock the UART and the arch timer on hardware. A wrong CPU
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mux/PLL would show later (cpufreq / peripheral rates), still to be checked.
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mux/PLL would show later (cpufreq / peripheral rates), still to be checked.
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## M3 — rootfs boot: NEXT
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## M3 — rootfs boot: ✅ DONE — the full WardenOS runs on the 6.18 kernel (2026-08-24)
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The M2 kernel mounts the 5.10 WardenOS rootfs_b but the userspace/module vermagic
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Adding the eMMC (`dw_mmc`) node to the DT was all M3 needed — the drivers are already
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mismatches (5.10 `.ko` won't load on 6.18). M3 = a lean RV1106 defconfig (drop
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in the config. On hardware:
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multi_v7), `dw_mmc`/`sdhci` DT wired to our CRU (eMMC already probes — `MMC0: HS200`),
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```
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and our Buildroot userspace rebuilt against 6.18. Then M4 display, M5 wifi, M6 rest.
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dwmmc_rockchip ffa90000.mmc: Version ID is 270a ← our dw_mmc bound
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mmc0: new HS200 MMC card ... mmcblk0: 8GTF4R 7.28 GiB ← eMMC at HS200 (198 MHz)
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mmcblk0: p1(env)...p10(rootfs_b)...p12(userdata) ← partitions enumerated
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EXT4-fs (mmcblk0p10): mounted ... VFS: Mounted root ← ext4 rootfs mounted
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Run /sbin/init as init process
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Starting warden-modbus / -mikrotik / -asic / -flared / Warden UI
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```
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A root shell over the serial console confirms it: `uname -a` → **`Linux warden-c8a3
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6.18.46 armv7l`**, with `warden-flared`, `warden-modbus`, `warden-mikrotik`,
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`warden-asic`, `warden-ui`, `warden-flight` all in `ps`. The eMMC node's ciu-drive/
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ciu-sample clocks come from `grf_cru`, so the M2 grf-cru fix was a prerequisite.
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The expected M4/M5 gaps show as clean failures: the out-of-tree 5.10 `aic8800`
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wifi/BT `.ko` won't load on 6.18 (vermagic — needs the driver ported, **M5**), and
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`warden-ui: no backlight device` (no display/VOP node yet — **M4**).
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## M4/M5/M6 — NEXT
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- **M4 display**: VOP2 + the RGB666 720×720 panel + GT911 touch + PWM backlight →
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the LVGL UI renders (the UI process already runs, it just has no framebuffer).
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- **M5 wifi**: port the AIC8800 SDIO driver to 6.18 (+ the Tier-1 fix) so wlan0/usb0
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come back; re-apply our 4 kernel patches.
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- **M6**: RGA, watchdog, HPMCU coprocessor, USB-OTG dual role.
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- **Cleanup**: a lean RV1106 defconfig to replace multi_v7 (shrinks the image, retires
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the fdt-high workaround) + our Buildroot userspace rebuilt on 6.18 (retires the
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vermagic-mismatched modules).
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## Upstream tracking (decision 2026-08-23)
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## Upstream tracking (decision 2026-08-23)
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Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream
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Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream
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@@ -39,9 +39,8 @@
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stdout-path = "serial2:115200n8";
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stdout-path = "serial2:115200n8";
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/*
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/*
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* earlycon with no baud = reuse the divisor the bootloader left in
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* earlycon with no baud = reuse the divisor the bootloader left in
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* uart2, so the first prints work regardless of our clock tree. The ttyS console is
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* uart2, so the first prints work regardless of our clock tree. The
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* pinned to 115200 to stay readable on the CP2102 bench adapter;
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* ttyS console rate (1.5M) is PORT-VERIFY against the board.
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* production WardenOS uses 1.5M.
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*/
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*/
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bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyS2,115200n8 earlyprintk rootwait";
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bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyS2,115200n8 earlyprintk rootwait";
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};
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};
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@@ -123,4 +122,24 @@
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clock-names = "baudclk", "apb_pclk";
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clock-names = "baudclk", "apb_pclk";
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status = "okay";
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status = "okay";
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};
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};
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/* M3: the eMMC (dw_mmc). Lets the kernel enumerate mmcblk0 and mount an
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* ext4 rootfs. ciu-drive/ciu-sample clocks come from grf_cru, so the
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* grf-clock-controller node above is a hard dependency. */
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emmc: mmc@ffa90000 {
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compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0xffa90000 0x4000>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>,
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<&grf_cru SCLK_EMMC_DRV>, <&grf_cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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max-frequency = <200000000>;
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rockchip,use-v2-tuning;
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bus-width = <8>;
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non-removable;
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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status = "okay";
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};
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};
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};
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