kernel: M2 earlycon build — full 6.18 zImage + minimal RV1106 board DT
M1 is complete (clk + pinctrl + mach compile clean); this reaches M2's build milestone. multi_v7_defconfig + configs/m2-earlycon.fragment builds an 11.8 MB zImage with clk-rv1106.o and pinctrl-rockchip.o (our rv1106 data) compiled into the full tree — no rv1106 warnings. dts/rv1106-warden-m2.dts (CPU, GIC-400, arch timer, 256 MiB RAM, GRF, the CRU, uart2 as snps,dw-apb-uart) compiles clean at W=1 with earlycon=uart8250,mmio32,0xff4c0000. Reproducible via build-m2.sh. Boot is the next step and is on-hardware/attended: package zImage + dtb, load on a bench unit with a recovery net, watch for the earlycon "it's alive". PORT-VERIFY before trusting a boot: DDR size/base, the CPU clock mux, console baud. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
This commit is contained in:
BFE Engineering
co-authored by
Claude Opus 4.8
Claude Opus 4.8
parent
435953799c
commit
d50934d048
@@ -48,11 +48,36 @@ RV1106:` in the 3 pull functions + the RK3568 drive-strength group; `rv1106_pin_
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- **Still PORT-VERIFY:** GPIO4 bank pin-count (`pin_banks` says 24, DT `gpio-ranges` says 32) —
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- **Still PORT-VERIFY:** GPIO4 bank pin-count (`pin_banks` says 24, DT `gpio-ranges` says 32) —
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carried from vendor unchanged; needs TRM/hardware.
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carried from vendor unchanged; needs TRM/hardware.
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## M1 — mach + defconfig: NEXT
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## M1 — mach: ✅ DONE
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Per the breadth survey's integration order: mach is a ~2-line DT-compat add to `rockchip.c`
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`mach-rockchip` RV1106/RV1103 SoC recognition added as a DT-compat entry (no
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(do NOT recreate the dropped `CPU_RV1106` symbol); then the minimal M2 defconfig; then the DT
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`CPU_RV1106` symbol recreated). Captured as `mach/0001-rv1106-soc-recognition.patch`.
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(SoC nodes transplant + board-specific PORT-VERIFY: console UART, boot media, panel timings);
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**M1 is complete: clk + pinctrl + mach all compile clean on 6.18.**
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then the first full kernel build toward an earlycon boot.
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## M2 — earlycon build: ✅ DONE (boot pending hardware)
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The first full kernel build with our SoC drivers, 2026-08-24:
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- **`multi_v7_defconfig` + `configs/m2-earlycon.fragment` builds an 11.8 MB zImage**
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with `clk-rv1106.o` (85732 B) and `pinctrl-rockchip.o` (173688 B, our rv1106 data)
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compiled *into the full tree* — no rv1106 warnings/errors. Reproducible via
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`build-m2.sh`.
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- **`dts/rv1106-warden-m2.dts` → `rv1106-warden-m2.dtb` compiles clean** (W=1, no dtc
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warnings). A deliberately minimal DT — CPU (cortex-a7), GIC-400, arch timer, 256 MiB
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RAM, GRF, the CRU (our clk-rv1106), and uart2 (`snps,dw-apb-uart`, the console) —
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with `earlycon=uart8250,mmio32,0xff4c0000` so the first print reuses the loader's
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divisor before any clock/pinctrl probe.
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**Still PORT-VERIFY before a boot is trusted:** memory size/base (256 MiB @ 0x0 assumed
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— the loader usually patches this); the CPU clock mux in clk-rv1106 (§M1 item 4); the
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console baud (1.5M assumed). A wrong DDR/clock value silently hangs before or just after
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earlycon.
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## M2 — boot: NEXT (on hardware)
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Package `zImage` + `rv1106-warden-m2.dtb` into a boot image and load on a bench unit
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(c8a3 / w7159, both with a proven recovery net), watching the debug UART — or the
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coprocessor USB console (R5) — for the earlycon "it's alive". A hang is expected to be
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one of the PORT-VERIFY values above; iterate with recovery ready. This is an attended
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step (brick-adjacent), not an unattended one.
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Then M3: `dw_mmc` DT + rootfs on our Buildroot userspace.
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## Upstream tracking (decision 2026-08-23)
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## Upstream tracking (decision 2026-08-23)
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Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream
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Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream
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@@ -69,10 +94,12 @@ on-hardware validation — which waits on c8a3's recovery and, ultimately, caref
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## Layout
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## Layout
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```
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```
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clk/
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clk/ clk-rv1106.c + rv1106-cru.h + framework-hooks patch (M1)
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clk-rv1106.c the ported driver (WIP, compiles to :427)
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pinctrl/ 0001-rv1106-pinctrl.patch (M1)
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rv1106-cru.h the clock-id dt-bindings header (staged)
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mach/ 0001-rv1106-soc-recognition.patch (M1)
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0001-rv1106-clk-framework-hooks.wip.patch Makefile/Kconfig/clk.h deltas vs vanilla 6.18
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dts/ rv1106-warden-m2.dts minimal earlycon board DT (M2)
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configs/ m2-earlycon.fragment defconfig delta over multi_v7 (M2)
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build-m2.sh reproducible M2 build (zImage + dtb)
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```
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```
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The full ported tree lives in `flare-edge/research/linux-6.18.46/` (scratch); this dir is
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The full ported tree lives in `flare-edge/research/linux-6.18.46/` (scratch); this dir is
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the durable, reviewable capture, to become a proper patch series as milestones land.
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the durable, reviewable capture, to become a proper patch series as milestones land.
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Executable
+41
@@ -0,0 +1,41 @@
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#!/usr/bin/env bash
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# build-m2.sh — reproducible M2 (earlycon) build of the RV1106 → 6.18 forward-port.
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#
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# Produces: a zImage with our ported SoC drivers, and rv1106-warden-m2.dtb.
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# Boot is a separate on-hardware step (see PORT-STATUS.md "M2 boot").
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#
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# Usage: KTREE=/path/to/linux-6.18.46 SDK_TC=/path/to/toolchain/bin ./build-m2.sh
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# Defaults match this workspace.
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set -euo pipefail
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FE="${FE:-<flare-edge>}"
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KTREE="${KTREE:-$FE/research/linux-6.18.46}"
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SDK_TC="${SDK_TC:-$FE/sdk/tools/linux/toolchain/arm-rockchip830-linux-uclibcgnueabihf/bin}"
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HERE="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
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# The SDK toolchain bakes absolute paths and needs `python` (not python3) + a
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# space-free PATH (see the flare-edge-sdk-path-compat note).
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export PATH="$SDK_TC:/usr/bin:/bin"
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export ARCH=arm
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export CROSS_COMPILE=arm-rockchip830-linux-uclibcgnueabihf-
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[ -d "$KTREE" ] || { echo "kernel tree not found: $KTREE" >&2; exit 1; }
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command -v python >/dev/null || { echo "need 'python' on PATH (SDK quirk)" >&2; exit 1; }
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# Stage our board DT into the tree if it drifted from the capture.
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install -m664 "$HERE/dts/rv1106-warden-m2.dts" \
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"$KTREE/arch/arm/boot/dts/rockchip/rv1106-warden-m2.dts"
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grep -q 'rv1106-warden-m2.dtb' "$KTREE/arch/arm/boot/dts/rockchip/Makefile" \
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|| sed -i 's/\trk3288-vyasa.dtb/\trk3288-vyasa.dtb \\\n\trv1106-warden-m2.dtb/' \
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"$KTREE/arch/arm/boot/dts/rockchip/Makefile"
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cd "$KTREE"
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make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE" multi_v7_defconfig
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./scripts/kconfig/merge_config.sh -m .config "$HERE/configs/m2-earlycon.fragment"
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make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE" olddefconfig
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make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE" -j"$(nproc)" zImage
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make ARCH=arm CROSS_COMPILE="$CROSS_COMPILE" rockchip/rv1106-warden-m2.dtb
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echo
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echo "== M2 build OK =="
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ls -la arch/arm/boot/zImage arch/arm/boot/dts/rockchip/rv1106-warden-m2.dtb
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@@ -0,0 +1,25 @@
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# M2 earlycon config fragment for the RV1106 → Linux 6.18 forward-port.
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#
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# Base: multi_v7_defconfig (PORT-STATUS confirms it configures and CLK_RV1106
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# wires in cleanly). Apply this fragment on top, then `make olddefconfig`:
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#
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# make ARCH=arm CROSS_COMPILE=arm-rockchip830-linux-uclibcgnueabihf- multi_v7_defconfig
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# ./scripts/kconfig/merge_config.sh -m .config kernel/.../configs/m2-earlycon.fragment
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# make ARCH=arm CROSS_COMPILE=... olddefconfig zImage
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#
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# This builds an 11.8 MB zImage with our ported SoC drivers compiled in
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# (clk-rv1106.o, pinctrl-rockchip.o with the rv1106 data) — verified 2026-08-24.
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# --- our ported RV1106 SoC drivers ---
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_CLK_RV1106=y
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CONFIG_PINCTRL_ROCKCHIP=y
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# --- console: mainline 8250_dw drives uart2 (snps,dw-apb-uart) ---
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_DW=y
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CONFIG_SERIAL_OF_PLATFORM=y
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# --- earlycon: the "it's alive" print, before clk/pinctrl probe ---
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CONFIG_SERIAL_EARLYCON=y
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@@ -0,0 +1,117 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Minimal RV1106 devicetree for the WardenOS 86-Panel — M2 "earlycon" bring-up
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* of the self-built Linux 6.18 forward-port (warden-sdk kernel/docs/bringup.md).
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*
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* Deliberately NOT the full vendor rv1106.dtsi: just the core needed to reach
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* "it's alive" on the debug UART — CPU, GIC, arch timer, RAM, the CRU (our
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* ported clk-rv1106), GRF, and uart2 (the console, driven by mainline 8250_dw).
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* earlycon writes uart2's MMIO directly at the bootloader's divisor, so it prints
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* before the clock/pinctrl drivers probe; the real ttyS console then needs the
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* CRU to hand out SCLK_UART2, which is exactly what this validates on hardware.
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*
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* PORT-VERIFY (must be checked against the TRM / on hardware before trusting a
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* boot — a wrong value here silently hangs the board):
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* - memory size/base (256 MiB @ 0x0 assumed for the 86-Panel; the loader
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* usually patches this — confirm against the real DDR init);
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* - uart2 is the console at 0xff4c0000 (matches the vendor ttyFIQ0 base);
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* - CRU needs no assigned-clocks here (PLLs keep their loader rates) — fine for
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* earlycon/console, revisit for the full clock tree.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/rv1106-cru.h>
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/ {
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model = "WardenOS 86-Panel (RV1106) — M2 earlycon bring-up";
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compatible = "rockchip,rv1106";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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serial2 = &uart2;
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};
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chosen {
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stdout-path = "serial2:1500000n8";
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/*
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* earlycon with no baud = reuse the divisor the bootloader left in
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* uart2, so the first prints work regardless of our clock tree. The
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* ttyS console rate (1.5M) is PORT-VERIFY against the board.
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*/
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bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyS2,1500000n8 earlyprintk rootwait";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MiB — PORT-VERIFY */
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&cru ARMCLK>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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gic: interrupt-controller@ff1f0000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0xff1f1000 0x1000>,
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<0xff1f2000 0x2000>,
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<0xff1f4000 0x2000>,
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<0xff1f6000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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grf: syscon@ff000000 {
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compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd";
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reg = <0xff000000 0x68000>;
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};
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cru: clock-controller@ff3a0000 {
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compatible = "rockchip,rv1106-cru";
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reg = <0xff3a0000 0x20000>;
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rockchip,grf = <&grf>;
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clocks = <&xin24m>;
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clock-names = "xin24m";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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uart2: serial@ff4c0000 {
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compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
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reg = <0xff4c0000 0x100>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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status = "okay";
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};
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};
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Reference in New Issue
Block a user