BFE EngineeringandClaude Opus 4.8
f3087399f2
The Linux 6.18.46 forward-port boots on the panel through our ported drivers, verified on the serial console: earlycon, arch timer (BogoMIPS calibrated), our clk-rv1106 CRU, pinctrl, and the mainline 8250 bound to uart2 clocked by our CRU (ttyS2 16550A), then rootfs mount. Two DT fixes got it past "Starting kernel": - fdt placed high (load=0x08000000) so the bloated multi_v7 zImage (~20 MiB decompressed) stops overrunning the DTB at 0xc00000 (was: r2=0, "invalid dtb"). - added the rockchip,rv1106-grf-cru node (grf-clock-controller child of grf) so clk-rv1106's grf_ctx isn't NULL (was: panic in rockchip_clk_register_branches). Console pinned to 115200 (readable on the CP2102 bench adapter; prod uses 1.5M). The boot-image format and the A/B _b-slot safe-test method (which auto-reverted to _a on every failed attempt) are in docs/m2-boot-on-c8a3.md. M3 next: lean defconfig + dw_mmc DT + our Buildroot userspace rebuilt on 6.18. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017wB8KB3MMQztRDXCMCkPrf
128 lines
8.1 KiB
Markdown
128 lines
8.1 KiB
Markdown
# RV1106 → 6.18 forward-port — live status
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Target: **Linux 6.18.46** (vanilla, `flare-edge/research/linux-6.18.46/`), forward-ported
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from the **vendor 5.10.160** tree, no plan44 code, built with our
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`arm-rockchip830-...-gcc 8.3` (confirmed: **gcc 8.3 builds 6.18 fine**).
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## Confirmed feasibility facts
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- gcc 8.3 (our SDK toolchain) compiles the 6.18 kernel — no toolchain bump needed to start.
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- `multi_v7_defconfig` (ARM + rockchip) configures; `CLK_RV1106=y` wires in cleanly.
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- rv1106's siblings **rv1126/rv1108 exist in both trees**, so their 5.10→6.18 delta is a
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working template for the framework API changes.
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## M1 — clock driver (`clk-rv1106.c`, 1294 lines): ✅ COMPILES CLEAN on 6.18
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Build-fix loop against 6.18 — `clk-rv1106.o` (85732 bytes) builds with no errors.
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Fixed (captured in `clk/`):
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1. **Kconfig + Makefile hooks** — added `CONFIG_CLK_RV1106` (mirrors CLK_RV1126).
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2. **CRU register macros** — ported all 55 `RV1106_*` register-accessor `#define`s from the
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vendor `clk.h` into 6.18's `clk.h` (mainline has none).
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3. **Header split** — `panic_notifier_list` moved to `<linux/panic_notifier.h>` (kernel
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5.18); added the include.
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4. **`rockchip_clk_register_armclk` signature change** — 5.10 took
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`(num_parents, parent_clk, alt_parent_clk)`; 6.18 takes `(parent_names[], num_parents)`
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and drives the mux from `reg_data.mux_core_main/alt`. Adapted the call to the 6.18 form
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using a parent-names array (sibling-delta from rv1126). **⚠ PORT-VERIFY**: the mux input
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list `{ "gpll","cpll","apll" }` and the `mux_core_main/alt=2` mapping are a best-effort
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from the 5.10 intent (main=apll) — they set the **CPU clock source**, so they must be
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checked against the RV1106 `CORECLKSEL_CON` register map (TRM) and validated on hardware
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before trusting a boot. A wrong mux silently breaks boot.
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5. **`CLK_FRAC_DIVIDER_NO_LIMIT`** — Rockchip downstream-only frac-divider flag (6 uses on
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the UART frac clocks); mainline has no min/max opt-out, mapped to 0 (default limit).
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**⚠ PORT-VERIFY**: UART fractional baud accuracy.
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## M1 — pinctrl (`pinctrl-rockchip.c/.h`): ✅ COMPILES CLEAN on 6.18
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`pinctrl-rockchip.o` (173688 bytes) builds no-errors. Transplanted from vendor 5.10 (effort S,
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zero API drift — the survey's assessment held): added `RV1106` to the type enum; a 159-line
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block of `RV1106_DRV/PULL/SMT_*` macros + 3 `rv1106_calc_*_reg_and_bit()` functions; `case
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RV1106:` in the 3 pull functions + the RK3568 drive-strength group; `rv1106_pin_banks[]` +
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`rv1106_pin_ctrl`; and the `rockchip,rv1106-pinctrl` of_device_id (dropping the vendor's
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`#ifdef CONFIG_CPU_RV1106` guard — mainline compiles all SoCs unconditionally). Captured as
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`pinctrl/0001-rv1106-pinctrl.patch`.
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- **PORT-VERIFY RESOLVED (iomux offsets):** the DRV/PULL/SMT per-bank offsets are confirmed by
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a THIRD independent source — the upstream Simon Glass v3 pinctrl patch. Its
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`rv1106_{drv,pull,smt}_offsets[]` match ours exactly once the 0x10000-strided per-bank IOC
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base is applied (e.g. vendor GPIO2 DRV `0x100C0` = `0x10000 + 0xc0`). Retires the "do not
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guess" iomux risk without hardware. (Note upstream uses per-bank IOC regmaps + low offsets;
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we use the vendor's full-offset form — same absolute register, both compile.)
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- **Still PORT-VERIFY:** GPIO4 bank pin-count (`pin_banks` says 24, DT `gpio-ranges` says 32) —
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carried from vendor unchanged; needs TRM/hardware.
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## M1 — mach: ✅ DONE
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`mach-rockchip` RV1106/RV1103 SoC recognition added as a DT-compat entry (no
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`CPU_RV1106` symbol recreated). Captured as `mach/0001-rv1106-soc-recognition.patch`.
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**M1 is complete: clk + pinctrl + mach all compile clean on 6.18.**
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## M2 — earlycon build: ✅ DONE (boot pending hardware)
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The first full kernel build with our SoC drivers, 2026-08-24:
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- **`multi_v7_defconfig` + `configs/m2-earlycon.fragment` builds an 11.8 MB zImage**
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with `clk-rv1106.o` (85732 B) and `pinctrl-rockchip.o` (173688 B, our rv1106 data)
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compiled *into the full tree* — no rv1106 warnings/errors. Reproducible via
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`build-m2.sh`.
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- **`dts/rv1106-warden-m2.dts` → `rv1106-warden-m2.dtb` compiles clean** (W=1, no dtc
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warnings). A deliberately minimal DT — CPU (cortex-a7), GIC-400, arch timer, 256 MiB
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RAM, GRF, the CRU (our clk-rv1106), and uart2 (`snps,dw-apb-uart`, the console) —
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with `earlycon=uart8250,mmio32,0xff4c0000` so the first print reuses the loader's
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divisor before any clock/pinctrl probe.
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**Still PORT-VERIFY before a boot is trusted:** memory size/base (256 MiB @ 0x0 assumed
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— the loader usually patches this); the CPU clock mux in clk-rv1106 (§M1 item 4); the
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console baud (1.5M assumed). A wrong DDR/clock value silently hangs before or just after
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earlycon.
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## M2 — boot: ✅ DONE — "it's alive" on warden-c8a3 (2026-08-24)
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The self-built **Linux 6.18.46 boots on real RV1106 hardware**, through our ported
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drivers, verified over the serial console. It reaches earlycon, the arch timer
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(BogoMIPS calibrated), **our `clk-rv1106` CRU driver**, pinctrl, and the mainline
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8250 bound to uart2 **clocked by our CRU** (`ttyS2 … 16550A`), then hands off to the
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real console and mounts a rootfs. See `../docs/m2-boot-on-c8a3.md` for the method
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(the A/B `_b`-slot safe-test framework worked first try) and the boot-image format
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(external-data FIT + resource, `mkimage -E -p 0x800`).
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Three bring-up bugs were found and fixed on hardware, all captured in the DT:
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1. **boot.img format** — rockchip U-Boot needs the external-data FIT + a `resource`
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(multi) sub-image with `rk-kernel.dtb`, else `No fit blob` / `Failed to load DTB`.
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2. **DTB overrun** — the bloated multi_v7 zImage decompresses to ~20 MiB and overran
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the DTB at 0xc00000, so the kernel got `r2=0` (`invalid dtb`). Fix: place the fdt
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high (`load=0x08000000`). A lean RV1106 defconfig would also fix this and is the
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right long-term move.
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3. **grf-cru NULL deref** — `clk-rv1106` registers a second branch set against a GRF
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clock-controller (`grf_ctx`), set only by a `rockchip,rv1106-grf-cru` node. The
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minimal DT omitted it → `grf_ctx` NULL → panic in `rockchip_clk_register_branches`.
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Fix: add the `grf-clock-controller` child to the grf syscon.
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**clk-rv1106 PORT-VERIFY (armclk mux, PLL rates) is now partially retired**: the CRU
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comes up far enough to clock the UART and the arch timer on hardware. A wrong CPU
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mux/PLL would show later (cpufreq / peripheral rates), still to be checked.
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## M3 — rootfs boot: NEXT
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The M2 kernel mounts the 5.10 WardenOS rootfs_b but the userspace/module vermagic
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mismatches (5.10 `.ko` won't load on 6.18). M3 = a lean RV1106 defconfig (drop
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multi_v7), `dw_mmc`/`sdhci` DT wired to our CRU (eMMC already probes — `MMC0: HS200`),
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and our Buildroot userspace rebuilt against 6.18. Then M4 display, M5 wifi, M6 rest.
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## Upstream tracking (decision 2026-08-23)
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Base stays the vendor forward-port (applies to 6.18; we control it). The unmerged upstream
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RV1106 series (~35 patches, "New" state, does NOT apply cleanly to 6.18 — pinctrl v3 failed at
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`pinctrl-rockchip.c:3390`) is used as a **correctness oracle** for boot-critical PORT-VERIFY
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values (already retired the iomux offsets) and tracked for eventual convergence when it merges.
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## Honest scope
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This is the first driver of ~120 in the RV1106 BSP. The clk port alone is a multi-cycle
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effort of the four delta classes above; the whole bring-up (M1–M6 in `../docs/bringup.md`)
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is a multi-month kernel effort. Progress is real and the method is proven; correctness of
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boot-critical pieces (clock mux, PLL rates, DDR, pinctrl iomux) requires the TRM and
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on-hardware validation — which waits on c8a3's recovery and, ultimately, careful bring-up.
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## Layout
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```
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clk/ clk-rv1106.c + rv1106-cru.h + framework-hooks patch (M1)
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pinctrl/ 0001-rv1106-pinctrl.patch (M1)
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mach/ 0001-rv1106-soc-recognition.patch (M1)
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dts/ rv1106-warden-m2.dts minimal earlycon board DT (M2)
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configs/ m2-earlycon.fragment defconfig delta over multi_v7 (M2)
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build-m2.sh reproducible M2 build (zImage + dtb)
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```
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The full ported tree lives in `flare-edge/research/linux-6.18.46/` (scratch); this dir is
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the durable, reviewable capture, to become a proper patch series as milestones land.
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